NXP Semiconductors MPC5566, Reference Manual

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Introduction
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 1-23
Table 1-4 shows the memory map for the MCU acting as a slave in a multi-master system from the point
of view of the external master.
Table 1-4. MPC5566 Family Slave Memory Map as Seen from an External Master
External Address Range
1
1
Only the lower 24 address signals (ADDR[8:31]) are available off-chip for external master accesses.
Size Use
0x0000_0000
2
–0x007F_FFFF
2
This address range is not part of the MPC5500 family slave memory map, rather it is shown to illustrate the addressing
scheme for off-chip accesses in multi-master mode.
8 MB N/A. Used for off-chip memory accesses
0x0080_0000–0x00AF_FFFF 3 MB Slave flash
3
3
The shadow row of the slave flash is not accessible by an external master.
0xB0_0000 – 0xBF_FFFF 1 MB Reserved
0x00C0_0000–0x00C1_FFFF 128 KB Slave internal SRAM
0x00C2_0000–0x00CF_FFFF 1 MB–128 KB (less total SRAM) Reserved
0x00D0_0000–0x00DF_FFFF 1 MB Reserved
0x00E0_0000–0x00EF_FFFF 1 MB Slave bridge A peripherals
0x00F0_0000–0x00FF_FFFF 1 MB Slave bridge B peripherals