Interrupt Controller (INTC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
10-29
interrupt request. The interrupt request is cleared by writing a 1 to the CLR
n
bit. Specific behavior includes
the following:
•
Writing a 1 to SET
n
leaves SET
n
unchanged at 0 but sets the flag bit (CLR
n
bit).
•
Writing a 0 to SET
n
has no effect.
•
Writing a 1 to CLR
n
clears the flag (CLR
n
) bit.
•
Writing a 0 to CLR
n
has no effect.
•
If a 1 is written to a pair of SET
n
and CLR
n
bits at the same time, the flag (CLR
n
) is set, regardless
of whether CLR
n
was asserted before the write.
The time from the write to the SET
n
bit to the time that the INTC starts to drive the interrupt request to the
processor is four clocks.
10.4.1.3
Unique Vector for Each Interrupt Request Source
Each peripheral and software settable interrupt request is assigned a hardwired unique 9-bit vector.
Software settable interrupts 0–7 are assigned vectors 0–7, respectively. The peripheral interrupt requests
are assigned vectors 8 to as high as needed to cover all of the peripheral interrupt requests.
10.4.2
Priority Management
The asserted interrupt requests are compared to each other based on their PRI
n
values in INTC priority
select registers (INTC_PSR0–INTC_PSR329). The result of that comparison also is compared to PRI in
INTC current priority register (INTC_CPR). The results of those comparisons are used to manage the
priority of the ISR being executed by the processor. The LIFO also assists in managing that priority.
10.4.2.1
Current Priority and Preemption
The priority arbitrator, selector, encoder, and comparator submodules shown in
are used to
compare the priority of the asserted interrupt requests to the current priority. If the priority of any asserted
peripheral or software settable interrupt request is higher than the current priority, then the interrupt request
to the processor is asserted. Also, a unique vector for the preempting peripheral or software settable
interrupt request is generated for INTC interrupt acknowledge register (INTC_IACKR), and if in hardware
vector mode, for the interrupt vector provided to the processor.
10.4.2.1.1
Priority Arbitrator Submodule
The priority arbitrator submodule compares all the priorities of all of the asserted interrupt requests, both
peripheral and software settable. The output of the priority arbitrator submodule is the highest of those
priorities. Also, any interrupt requests which have this highest priority are output as asserted interrupt
requests to the request selector submodule.
10.4.2.1.2
Request Selector Submodule
If only one interrupt request from the priority arbitrator submodule is asserted, then it is passed as asserted
to the vector encoder submodule. If multiple interrupt requests from the priority arbitrator submodule are
asserted, then only the one with the lowest vector is passed as asserted to the vector encoder submodule.
Summary of Contents for MPC5566
Page 81: ...Introduction MPC5566 Microcontroller Reference Manual Rev 2 1 24 Freescale Semiconductor...
Page 135: ...Signal Description MPC5566 Microcontroller Reference Manual Rev 2 2 54 Freescale Semiconductor...
Page 189: ...Reset MPC5566 Microcontroller Reference Manual Rev 2 4 20 Freescale Semiconductor...
Page 603: ...Flash Memory MPC5566 Microcontroller Reference Manual Rev 2 13 38 Freescale Semiconductor...
Page 609: ...SRAM MPC5566 Microcontroller Reference Manual Rev 2 14 6 Freescale Semiconductor...
Page 1073: ...MPC5566 Microcontroller Reference Manual Rev 2 22 36 Freescale Semiconductor...
Page 1185: ...Nexus MPC5566 Microcontroller Reference Manual Rev 2 25 92 Freescale Semiconductor...
