NXP Semiconductors MPC5566, Reference Manual

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Revision history
MPC5566 Reference Manual Addendum, Rev. 2
Freescale Semiconductor 9
Table 2. Revision history
Revision Substantive changes Date of release
1.0 • Initial release. Corrected errors in chapter 12, “External Bus Interface (EBI).” 10/2009
2.0 • Corrected errors in chapter 9, “Enhanced Direct Memory Access (eDMA).”
• Corrected errors in chapter 5, “Peripheral Bridge (PBRIDGE A and PBRIDGE
B).”
• Corrected peripheral bridge name errors in appendix A, “MPC5566 Register
Map.”
• Corrected unified channel block diagram in chapter 16, “Enhanced Modular
Input/Output Subsystem (eMIOS).
• Clarified the description in Section 9.4.1, “eDMA Microarchitecture”.
• Clarified the description in Section 9.3.1.13, “eDMA Interrupt Request
Registers (EDMA_IRQRL).
• Clarified note in the INTC Interrupt Acknowledge Register
• Added a note in the INTC Memory Map table
• Clarified note at the end of the MPC5566 Interrupt Request Sources table
• Added a paragraph to the Section 10.4.2.1.4, “Priority Comparator
Submodule”
• Updated Section 10.5.5.2, “Ensuring Coherency”
• Corrected table “PCR218 PA Field Definition” and figure “AN[15]_FCK Pad
Configuration Register (SIU_PCR218)” and note 2 under figure.
• Deleted the last note in PREDIV field description of Synthesizer Control
Register (FMPLL_SYNCR) that states
05/2012