Nexus
MPC5566 Microcontroller Reference Manual, Rev. 2
25-6
Freescale Semiconductor
25.2.1
Detailed Signal Descriptions
This section describes each of the signals listed in
in more detail.
25.2.1.1
Event Out (EVTO
)
EVTO is an output pin that is asserted upon breakpoint occurrence to provide breakpoint status indication
or to signify that an event has occurred. The EVTO output of the NPC is generated based on the values of
the individual EVTO signals from all Nexus modules that implement the signal.
25.2.1.2
Event In (EVTI
)
EVTI is used to initiate program and data trace synchronization messages or to generate a breakpoint.
EVTI is edge-sensitive for synchronization and breakpoint generation.
25.2.1.3
Message Data Out (MDO[3:0] or [11:0])
Message data out (MDO) are output pins used for uploading OTM, BTM, DTM, and other messages to
the development tool. The development tool should sample MDO on the rising edge of MCKO. The width
of the MDO bus used is determined by the Nexus PCR[FPM] configuration.
Following a power-on reset, MDO[0] remains asserted until power-on reset is exited and the system clock
achieves lock.
25.2.1.4
Message Start/End Out (MSEO[1:0])
MSEO[1:0] are output pins that indicates when a message on the MDO pins has started, when a variable
length packet has ended, or when the message has ended. The development tool should sample the MSEO
pins on the rising edge of MCKO.
25.2.1.5
Ready (RDY)
RDY is an output pin that indicates when a device is ready for the next access.
25.2.1.6
JTAG Compliancy (JCOMP)
The JCOMP signal enables or disables the TAP controller. The TAP controller is enabled when JCOMP
asserted, otherwise the TAP controller remains in reset.
25.2.1.7
Test Data Output (TDO)
The TDO pin transmits serial output for instructions and data. TDO is tri-stateable and is actively driven
in the SHIFT-IR and SHIFT-DR controller states. TDO is updated on the falling edge of TCK and sampled
by the development tool on the rising edge of TCK.
25.2.1.8
Test Clock Input (TCK)
The TCK pin is used to synchronize the test logic and control register access through the JTAG port.
Summary of Contents for MPC5566
Page 81: ...Introduction MPC5566 Microcontroller Reference Manual Rev 2 1 24 Freescale Semiconductor...
Page 135: ...Signal Description MPC5566 Microcontroller Reference Manual Rev 2 2 54 Freescale Semiconductor...
Page 189: ...Reset MPC5566 Microcontroller Reference Manual Rev 2 4 20 Freescale Semiconductor...
Page 603: ...Flash Memory MPC5566 Microcontroller Reference Manual Rev 2 13 38 Freescale Semiconductor...
Page 609: ...SRAM MPC5566 Microcontroller Reference Manual Rev 2 14 6 Freescale Semiconductor...
Page 1073: ...MPC5566 Microcontroller Reference Manual Rev 2 22 36 Freescale Semiconductor...
Page 1185: ...Nexus MPC5566 Microcontroller Reference Manual Rev 2 25 92 Freescale Semiconductor...
