NXP Semiconductors MPC5566, Reference Manual

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Nexus
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 25-13
exiting power-on reset. After the system clock is locked, MDO0 is negated and tools may begin Nexus
configuration. Loss of lock conditions that occur subsequent to the exit of power-on reset and the initial
lock of the system clock do not cause a Nexus reset, and therefore do not result in MDO0 driven high.
25.5 Nexus Port Controller (NPC)
The Nexus port controller (NPC) is that part of the NDI that controls access and arbitration of the device’s
internal Nexus modules. The NPC contains the port configuration register (PCR) and the device
identification register (DID). The contents of the NPC DID are the same as the JTAGC device
identification register.
25.5.1 Overview
The device incorporates multiple modules that require development support. Each of these modules
implements a development interface based on the IEEE-ISTO 5001-2001 standard and must share the
input and output ports that interface with the development tool. The NPC controls the usage of these ports
in a manner that allows the individual modules to share the ports, while appearing to the development tool
as a single module.
25.5.2 Features
The NPC performs the following functions:
• Controls arbitration for ownership of the Nexus auxiliary output port
• Nexus device identification register and messaging
• Generates MCKO enable and frequency division control signals
• Controls sharing of EVTO
• Control of the device-wide debug mode
• Generates asynchronous reset signal for Nexus modules based on JCOMP input, censorship status,
and power-on reset status
• System clock locked status indication via MDO[0] during Nexus reset
• Provides Nexus support for censorship mode
25.6 Memory Map/Register Definition
This section provides a detailed description of the NPC registers accessible to the end user. Individual
bit-level descriptions and reset states of the registers are included.
25.6.1 Memory Map
Table 25-9 shows the NPC registers by index values. The registers are not memory-mapped and can only
be accessed via the TAP. The NPC does not implement the client select control register because the value
does not matter when accessing the registers. The bypass register (refer to
Section 25.6.2.1, “Bypass
Register ”) and instruction register (refer to Section 25.6.2.2, “Instruction Register ”) have no index values.
These registers are not accessed in the same manner as Nexus client registers.