NXP Semiconductors MPC5566, Reference Manual

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System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 6-107
Writes to the SIU_GPDO n registers have no effect when a primary or alternate function is assigned.
Table 6-147 describes the PDO n bit field in the general purpose data output registers:
6.3.1.160 GPIO Pin Data Input Registers 0–213 (SIU_GPDI n )
The 8-bit read-only SIU_GPDI n registers defined in Figure 6-160 each specify the input state for the
function assigned to the GPDI[ n ] pin. The n notation in the214 SIU_GPDI n register names relate to the
[ n ] in GPIO[ n ] signal name. For example, SIU_GPDI0 contains the PDI0 bit for CS[0]_GPIO[0]; and
SIU_GPDI213 contains the PDI213 bit for WKPCFG_GPIO[213]. The GPDI address for a particular pin
is the GPIO number plus an offset of SI 0x0800. Gaps exist in the memory where GPIO pins
are not implemented in the package.
Software reads the SIU_GPDI n registers to get the input state of the external GPIO pin. Each GPDI
register contains the input state of one external GPIO pin. If a GPDI register is configured as output, and
the input buffer enable bit is set to one in the PCR register, the SIU_GPDI
n register reflects the state of the
output pin.
Address: SI 0x0600 R/W
0 1 2 3 4 5 6 7
R 0 0 0 0 0 0 0 0
W PDO n
Reset 0 0 0 0 0 0 0 0
Figure 6-159. General Purpose Data Output (GPDO) Registers 0–213 (SIU_GPDO n )
Table 6-147. SIU_GPDO n Field Descriptions
Name Description
PDO n Pin data out. Stores the data to drive out the external GPIO. If the register is read,
it returns the value written.
0 V
OL
is driven on the external GPIO pin when the pin is configured as an output.
1 V
OH
is driven on the external GPIO pin when the pin is configured as an output.
Address: SI 0x0800 R/O
0 1 2 3 4 5 6 7
R 0 0 0 0 0 0 0 PDI n
W
Reset 0 0 0 0 0 0 0 0
Figure 6-160. General Purpose Data Input (GPDI) Registers 0–213 (SIU_GPDI n )