NXP Semiconductors MPC5566, Reference Manual

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e200z6 Core Complex
MPC5566 Microcontroller Reference Manual, Rev. 2
3-28 Freescale Semiconductor
13 DSB
Disable store buffer
0 = store buffer enabled
1 = store buffer disabled
14 DSTRM
Disable streaming
0 = streaming is enabled
1 = streaming is disabled
15 CPE
Cache parity enable
0 = parity checking is disabled
1 = parity checking is enabled
16–20 — Reserved
21 CUL
Cache unable to lock
Indicates a lock set instruction was not effective in locking a cache line. This bit
is set by hardware on an “unable to lock” condition (other than lock overflows),
and will remain set until cleared by software writing 0 to this bit location.
22 CLO
Cache lock overflow
Indicates a lock overflow (overlocking) condition occurred. This bit is set by
hardware on an “overlocking” condition, and will remain set until cleared by
software writing 0 to this bit location.
23 CLFC
Cache lock bits flash clear
When written to a 1, a cache lock bit flash clear operation is initiated by hardware.
After this is complete, this bit is reset to 0. Writing a 1 during a flash clear
operation results in an undefined operation. Writing a 0 during a flash clear
operation is ignored. Cache lock bits flash clear operations require
approximately 134 cycles to complete. Clearing occurs regardless of the enable
(CE) value.
24–26 — Reserved
27 CORG
Cache organization
0 = The cache is organized as 128 sets and 8 ways
1 = The cache is organized as 256 sets and 4 ways.
Selecting CORG = 1 helps minimize power consumption.
28 — Reserved
29 CABT
Cache operation aborted
Indicates a cache invalidate or a cache lock bits flash clear operation was aborted
prior to completion. This bit is set by hardware on an aborted condition, and will
remain set until cleared by software writing 0 to this bit location.
30 CINV
Cache invalidate
0 = No cache invalidate
1 = Cache invalidation operation
When written to a 1, a cache invalidation operation is initiated by hardware. After
this is complete, this bit is reset to 0. Writing a 1 while an invalidation operation is in
progress will result in an undefined operation. Writing a 0 to this bit while an
invalidation operation is in progress will be ignored. Cache invalidation operations
require approximately134 cycles to complete. Invalidation occurs regardless of the
enable (CE) value.
Table 3-9. L1CSR0 Field Descriptions (continued)
Bits Name Description