NXP Semiconductors MPC5566, Reference Manual

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Addendum for Revision 2.0
MPC5566 Reference Manual Addendum, Rev. 2
Freescale Semiconductor 5
Figure 17-13, “Unified
Channel Block Diagram”/Page
17-26
Reverse the arrow between the "Programmable Filter" and "Edge Detect".
Section 9.3.1 eDMA
Microarchitecture/ Page 9-33
In the Memory controller sub-bullet, delete the line "The hooks to a BIST controller for the local
TCD memory are included in this module".
Section 9.2.2.13, “eDMA
Interrupt Request Registers
(EDMA_IRQRH,
EDMA_IRQRL)”/ Page 9-19
In the third paragraph, remove the last line "without the need to perform a read-modify-write
sequence to the EDMA_IRQRH and EDMA_IRQRL".
Section 8.3: Initialization and
Application Information/Page
8-15
Change the sentence, “There are eight ECC check bits for each 64-bit data doubleword” to the
following:
• SRAM—Eight ECC check bits for each 64-bit SRAM data doubleword.
• Flash—Eight ECC check bits for each 64-bit flash data doubleword.
Table 6-152, “SIU_DISR Field
Descriptions”/ Page 6-113
• Bit 14-15–TRIGSELB: Correct the input select description as follows:
00: Replace the term “Invalid value” with “No Trigger”
• Bit 22-23–TRIGSELC: Correct the input select description as follows:
00: Replace the term “Invalid value” with “No Trigger”
• Bit 30-31–TRIGSELD: Correct the input select description as follows:
00: Replace the term “Invalid value” with “No Trigger”
Table 1. MPC5566RM Rev 2.0 addendum
Location Description