NXP Semiconductors MPC5566, Reference Manual

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e200z6 Core Complex
MPC5566 Microcontroller Reference Manual, Rev. 2
3-26 Freescale Semiconductor
When WAM is set to 1, ways disabled for instruction access are not affected by the icbt , icblc , icbtls , and
icbi instructions. Ways disabled for data accesses are not affected by the dcba , dcbf , dcbi , dcblc , dcbst ,
dcbt , dcbtls , dcbtst , dcbtstls , and dcbz instructions. Cache control operations using L1CSR0[CINV] and
L1FINV0 operations are not affected by the WAM setting and proceed normally.
3.3.2.5 L1 Cache Control and Status Register 0 (L1CSR0)
The L1 cache control and status register 0 (L1CSR0) is a 32-bit register. The L1CSR0 register is accessed
using a
mfspr or mtspr instruction. The SPR number for L1CSR0 is 1010 in decimal. The L1CSR0
register is shown in Figure 3-16 . The correct sequence necessary to change the value of LSCSR0 is:
1. msync
2. isync
3. mtspr L1CSR0
The L1CSR0 bits are described in Table 3-9 .
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
WID
WDD
AW
ID
A
W
DD
WA
M
CWM
DPB DSB
DSTR
M
CPE
0
CU
L
CL
O
CLFC
0
CO
R
G
0
CABT
CINV
CE
SPR–1010; Read/Write; Reset–0x0
Figure 3-16. L1 Cache Control and Status Register 0 (L1CSR0)
Table 3-9. L1CSR0 Field Descriptions
Bits Name Description
0:3
WID
Way instruction disable.
0 = The corresponding way is available for replacement by instruction miss line
fills.
1 = The corresponding way is not available for replacement by instruction miss
line fills.
Bit 0 corresponds to way 0.
Bit 1 corresponds to way 1.
Bit 2 corresponds to way 2.
Bit 3 corresponds to way 3.
The WID and WDD bits can be used for locking ways of the cache, and also are used
in determining the replacement policy of the cache.