NXP Semiconductors MPC5566, Reference Manual

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Introduction
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 1-5
– Supports assigning cache as instruction or data only on a per-way basis
– Supports tag and data parity
— Vectored interrupt support
— Interrupt latency is less than 70 ns @132 MHz (measured from interrupt request to execution
of first instruction of interrupt exception handler)
— Reservation instructions for implementing read-modify-write constructs
(internal SRAM and flash)
— Signal processing engine (SPE) auxiliary processing unit (APU) operating on 64-bit GPRs
— Floating point
– IEEE
®
754 compatible with software wrapper
– Single precision in hardware, double precision with software library
– Conversion instructions between single precision floating point and fixed point
— Long cycle time instructions, except for guarded loads. Do not increase interrupt latency in the
MPC5566 to reduce latency; long cycle time instructions are aborted upon interrupt requests.
— Extensive system development support through Nexus debug module
• System bus crossbar switch (XBAR)
— Four master ports, five slave ports
— 32-bit address bus, 64-bit data bus
— Simultaneous accesses from different masters to different slaves (there is no clock penalty
when a parked master accesses a slave)
• Enhanced direct memory access (eDMA) controller
— 64 channels support independent 8-, 16-, 32-bit single value or block transfers
— Supports variable sized queues and circular queues
— Source and destination address registers are independently configured to post-increment or
remain constant
— Each transfer is initiated by a peripheral, CPU, or eDMA channel request
— Each eDMA channel can optionally send an interrupt request to the CPU on completion of a
single value or block transfer
• Interrupt controller (INTC)
— 329 interrupt request registers
1
– 298 peripheral interrupt requests
– 8 software settable sources
– 26 reserved
— Unique 9-bit vector per interrupt source
— 16 priority levels with fixed hardware arbitration within priority levels for each interrupt source
— Priority elevation for shared resources
1. Although this device has a maximum of 329 interrupts, the logic requires that the total number of interrupts be divisible by four.
Therefore, the total number of interrupts specified for this device is 332.