NXP Semiconductors MPC5566, Reference Manual

Page: 476 / 1268

Frequency Modulated Phase Locked Loop and System Clocks (FMPLL)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 11-21
11.4.1.3.1 External Bus Clock (CLKOUT)
The external bus clock (CLKOUT) divider can be programmed to divide the system clock by two or four
based on the settings of the EBDF bit field in the SIU external clock control register (SIU_ECCR). The
reset value of the EBDF selects a CLKOUT frequency of one half of the system clock frequency. The EBI
supports gating of the CLKOUT signal when there are no external bus accesses in progress. Refer to the
Chapter 6, “System Integration Unit (SIU) ” for more information on CLKOUT.
The hold-time for the external bus pins can be changed by writing to the external bus tap select (EBTS)
bit in the SIU_ECCR. Refer to
Chapter 6, “System Integration Unit (SIU) ” for more information.
11.4.1.3.2 Nexus Message Clock (MCKO)
The Nexus message clock (MCKO) divider can be programmed to divide the system clock by two, four or
eight based on the MCKO_DIV bit field in the port configuration register (PCR) in the Nexus port
controller (NPC). The reset value of the MCKO_DIV selects an MCKO clock frequency one half of the
system clock frequency. The MCKO divider is configured by writing to the NPC through the JTAG port.
Refer to
Chapter 25, “Nexus Development Interface ” for more information.
11.4.1.3.3 Engineering Clock (ENGCLK)
The engineering clock (ENGCLK) divider can be programmed to divide the system clock by factors from
2 to 126 in increments of two. The ENGDIV bit field in the SIU_ECCR determines the divide factor. The
reset value of ENGDIV selects an ENGCLK frequency of system clock divided by 32.
11.4.1.3.4 FlexCAN_ x Clock Domains
The FlexCAN modules have two distinct software controlled clock domains. One of the clock domains is
always derived from the system clock. This clock domain includes the message buffer logic. The source
for the second clock domain can be either the system clock or a direct feed from the oscillator pin
EXTAL_EXTCLK. The logic in the second clock domain controls the CAN interface pins. The CLK_SRC
bit in the FlexCAN CTRL register selects between the system clock and the oscillator clock as the clock
source for the second domain. Selecting the oscillator as the clock source ensures very low jitter on the
CAN bus. System software can gate both clocks by writing to the MDIS bit in the FlexCAN MCR register.
Figure 11-1 shows the two clock domains in the FlexCAN modules.
Refer to Chapter 22, “FlexCAN2 Controller Area Network ” for more information on the FlexCAN
modules.
11.4.1.3.5 FEC Clocks
The FEC TX_CLK and FEC_RX_CLK are inputs. An external source provides the clocks to these pins.