NXP Semiconductors MPC5566, Reference Manual

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Calibration
MPC5566 Microcontroller Reference Manual, Rev. 2
B-6 Freescale Semiconductor
Refer to Section B.8.1, “Enabling Calibration Reflection Suppression ,” for when to set SIU_CCR[CRSE]
or leave it in its reset negated state.
B.8 Application Information
B.8.1 Enabling Calibration Reflection Suppression
Set SIU_CCR[CRSE] to suppress reflections when calibrating. The calibration reflection suppression
logic for an output that does not return to a negated state at the end of an access can introduce a small glitch
on the output at the end of the access. The glitch does not interfere with the output valid or hold times.
However, keep SIU_CCR[CRSE] in its reset negated state when not calibrating to prevent a glitch on the
non-calibration bus outputs.
B.8.2 Communication With Development Tool Using I/O
The development tool can require some I/Os for communication between the MCU and the development
tool on the VertiCal connector. ETRIG[0:1] and GPIO[205] are available only in the 416 pin package.
Because the application can not use these pins in the 208 and 324 pin packages, they can be used for
development tool use in a VertiCal connector. Using ETRIG[1] and GPIO[205] still leaves ETRIG[0] for
the application in the 416 package.
B.8.3 Matching Access Delay to Internal Flash With Calibration Memory
One use of VertiCal in the Automotive environment is engine calibration. For this application, an SRAM
Top Board is added onto the VertiCal connector. This allows the engine calibrator to modify settings in
SRAM, possibly using the Nexus interface or even by using the SCI port or a CAN interface.
Refer to Table 13-3 “Internal Flash External Emulation Mode.”
After the data is calibrated, it can be copied into the internal flash. The internal flash can be accessed faster
than the calibration memory, and the change in calibration data access time can change the overall system
performance. To mitigate this change in system performance, the internal flash memory includes a feature
that allows accesses to portions of the flash to be slowed down by adding extra wait states. This is done by
multiply mapping the internal flash at different locations with different number of wait states. For example,
the physical address of the flash array is 0x0000_0000 to 0x00FF_FFFF (depending on array size). That
same flash data can be accessed at address 0x0100_0000 to 0x01FF_FFFF but accesses are one clock cycle
slower. That same flash data can be accessed at addresses 0x0200_0000 to 0x02FF_FFFF but accesses are
two clock cycles slower. This pattern is repeated through the memory map to addresses 0x1F00_0000 to
0x1FFF_FFFF where accesses are 31 clock cycles slower.
The application can use this feature by mapping the calibration data to a region of the flash memory that
has access timing to match the timing of the calibration RAM used when calibrating the data. This
remapping of calibration data can be achieved by either using the translation feature of the MMU or
rebuilding the code with a modified link file.