NXP Semiconductors MPC5566, Reference Manual

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External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
12-64 Freescale Semiconductor
Figure 12-41 and Figure 12-42 describe read and write cycles from an external master accessing internal
space in the MCU. The minimal latency for an external master access is three clock cycles. The actual
latency of an external to internal cycle varies depending on which internal module is being accessed and
how much internal bus traffic is going on at the time of the access.
Figure 12-41. External Master Read from MCU
Receive bus grant and bus busy
negated for second cycle
Assert BB drive address
and assert TS
Using the internal arbiter
CLKOUT
BR (input)
RD_WR
TSIZ[0:1]
BDIP
BG
BB
ADDR[8:31]
DATA[0:31]
TS (input)
Minimum
two wait states
If the external master is another MCU with this EBI, then BB and other control pins are turned off
*
*
as shown due to use of latched TA internally. This extra cycle is not required by the slave EBI.
DATA is valid
TA (output)