NXP Semiconductors MPC5566, Reference Manual

Page: 237 / 1268

System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
6-34 Freescale Semiconductor
Refer to Table 6-19 for bit field definitions. Table 6-30 lists the PA fields for
DATA[25]_FEC_RX_DV_GPIO[53].
6.3.1.30 Pad Configuration Registers 54 (SIU_PCR54)
The SIU_PCR54 register controls the function, direction, and electrical attributes of
DATA[26]_FEC_TX_EN_GPIO[54].
Figure 6-31. DATA[26]_FEC_TX_EN_GPIO[54] Pad Configuration Registers (SIU_PCR54)
Refer to Table 6-19 for bit field definitions. Table 6-31 lists the PA fields for
DATA[26]_FEC_TX_EN_GPIO[54].
Table 6-30. PCR53 PA Field Descriptions
PA Field Pin Function
0b00 GPIO[53]
0b01 DATA[25]
0b10 FEC_RX_DV
0b11 DATA[25]
Address: Base + 0x00AC Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
PA OBE
1
1
When configured as DATA[26] or FEC_TX_EN, the OBE bit has no effect.
When configured as GPDO, set the OBE bit to 1.
IBE
2
2
When the pad is configured as an output, set the IBE bit to 1 to reflect the pin state in the GPDI register.
Clear the IBE bit to 0 to reduce power consumption. When configured as GPDI, set the IBE bit to 1.
DSC ODE
3
3
When configured as DATA[26] or FEC_TX_EN, clear the ODE bit to 0.
HYS
4
4
If external master operation is enabled, clear the HYS bit to 0.
0 0
WPE
5
5
Refer to the EBI section for weak pullup settings when configured as DATA[26] or FEC_TX_EN.
WPS
5
W
RESET: 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1
Table 6-31. PCR54 PA Field Descriptions
PA Field Pin Function
0b00 GPIO[54]
0b01 DATA[26]
0b10 FEC_RX_DV
0b11 DATA[26]