NXP Semiconductors MPC5566, Reference Manual

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Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 17-63
Figure 17-46 shows the timing for the A1 and B1 loading. A1 and B1 use the same signal to trigger a load,
which is generated based on the selected counter reaching one. This event is defined as the cycle boundary.
The load signal pulse has the duration of one system clock cycle and occurs at the first system clock period
of every cycle of the counter. If A2 and B2 are written within cycle (
n ), their values are loaded into A1 and
B1, respectively, at the first clock of cycle ( n +1). The update disable bits, EMIOS_OUDR, can be used to
control the update of these registers, thus allowing the delay of A1 and B1 update for synchronization
purposes.
During the load pulse A1 still holds its old value, which is updated on the following system clock cycle.
During the A1 load pulse, an internal by-pass allows the use of A2 instead of A1 for matches if A2 is either
0 or 1, thus allowing matches to be generated even when A1 is being loaded. This approach allows a
uniform channel operation for any A2 value, including 1 and 0.
In Figure 17-46 it is assumed that the channel and global prescalers are set to one, meaning that the channel
internal counter transition at every system clock cycle. FLAGs can be generated only on B1 matches when
MODE[5] is cleared, or on both A1 and B1 matches when MODE[5] is set. Since B1 FLAG occurs at the
cycle boundary, this flag can be used to indicate that A2 or B2 data written on cycle (
n ) were loaded to A1
or B1, respectively, thus generating matches in cycle ( n +1).
Figure 17-46. eMIOS OPWFMB Mode Example — A1/B1 Updates and Flags
Cycle n Cycle n+1 Cycle n+2
A1 value
B1 value
B2 value
0x000008
0x000002
0x000006
0x000008
0x000001
EMIOS_CCNTR n
0x000004
0x000006
MODE[0] = 1
A2 value
0x000002 0x000004 0x000006
0x000002
0x000004
0x000006
0x000008 0x000006
Output flip-flop
Write to B2
Match A1 Match B1
Match B1
A1/B1 load signal
Due to B1 match
FLAG set event
cycle n-1
Time
Write to A2
Match A1
Write to A2 Match B1
EDPOL = 0