NXP Semiconductors MPC5566, Reference Manual

Page: 643 / 1268

Fast Ethernet Controller (FEC)
MPC5566 Microcontroller Reference Manual, Rev. 2
15-34 Freescale Semiconductor
The 7-wire serial mode interface (RCR[MII_MODE] = 0) operates in what is generally referred to as the
“AMD” mode. 7-wire mode connections to the external transceiver are shown in
Table 15-33 .
15.4.6 FEC Frame Transmission
The Ethernet transmitter is designed to work with almost no intervention from software. Once
ECR[ETHER_EN] is asserted and data appears in the transmit FIFO, the Ethernet MAC is able to transmit
onto the network.
When the transmit FIFO fills to the watermark (defined by the TFWR), the MAC transmit logic asserts
FEC_TX_EN and start transmitting the preamble (PA) sequence, the start frame delimiter (SFD), and then
the frame information from the FIFO. However, the controller defers the transmission if the network is
busy (FEC_CRS asserts). Before transmitting, the controller waits for carrier sense to become inactive,
then determines if carrier sense stays inactive for 60 bit times. If so, the transmission begins after waiting
an additional 36 bit times (96 bit times after carrier sense originally became inactive). See
Section 15.4.14.1, “Transmission Errors ” for more details.
Transmit Error FEC_TX_ER
Collision FEC_COL
Carrier Sense FEC_CRS
Receive Clock FEC_RX_CLK
Receive Data Valid FEC_RX_DV
Receive Data FEC_RXD[3:0]
Receive Error FEC_RX_ER
Management Data Clock FEC_MDC
Management Data Input/Output FEC_MDIO
Table 15-33. 7-Wire Mode Configuration
Signal Description FEC Signal
Transmit Clock
FEC_ TX_CLK
Transmit Enable
FEC_ TX_EN
Transmit Data
FEC_ TXD0
Collision
FEC_ COL
Receive Clock
FEC_ RX_CLK
Receive Data Valid
FEC_ RX_DV
Receive Data
FEC_ RXD0
Table 15-32. MII Mode (continued)
Signal Description EMAC Signal