
Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
19-48
Freescale Semiconductor
Table 19-34. On-Chip ADC Field Descriptions: Conversion Command Message Format
Field
Description
0
EOQ
End-of-queue. Asserted in the last command of a command queue to indicate to the eQADC that a scan of the
queue is completed. EOQ instructs the eQADC to reset its current CFIFO transfer counter value (TC_CF) to 0.
Depending on the CFIFO operating mode, the CFIFO status changes when it detects when the EOQ bit on the
last transferred command is asserted. Refer to
Section 19.4.3.5, “CFIFO Scan Trigger Modes
,” for details.
0 Not the last entry of the command queue.
1 Last entry of the command queue.
Note:
If both the pause and EOQ bits are asserted in the same command message the respective flags are set,
but the CFIFO status changes as if only the EOQ bit were asserted.
1
PAUSE
Pause. Allows software to create sub-queues within a command queue. When the eQADC completes the
transfer of a command with an asserted pause bit, the CFIFO enters the WAITING FOR TRIGGER state. Refer
to
Section 19.4.3.6.1, “CFIFO Operation Status
,” for a description of the state transitions. The pause bit is only
valid when CFIFO operation mode is configured to single or continuous-scan edge trigger mode.
0 Do not enter WAITING FOR TRIGGER state after transfer of the current command message.
1 Enter WAITING FOR TRIGGER state after transfer of the current command message.
Note:
If both the pause and EOQ bits are asserted in the same command message the respective flags are set,
but the CFIFO status changes as if only the EOQ bit were asserted.
2–4
Reserved.
5
EB
External buffer bit. A negated EB bit indicates that the command is sent to an on chip ADC.
0 Command is sent to an internal buffer.
1 Command is sent to an external buffer.
6
BN
Buffer number. For internal commands, ADCs 1 and 0 can be internal or external depending on the EBI bit
setting.
0 Message ADC 0.
1 Message ADC 1.
7
CAL
Calibration. Indicates if the returning conversion result must be calibrated.
0 Do not calibrate conversion result.
1 Calibrate conversion result.
Summary of Contents for MPC5566
Page 81: ...Introduction MPC5566 Microcontroller Reference Manual Rev 2 1 24 Freescale Semiconductor...
Page 135: ...Signal Description MPC5566 Microcontroller Reference Manual Rev 2 2 54 Freescale Semiconductor...
Page 189: ...Reset MPC5566 Microcontroller Reference Manual Rev 2 4 20 Freescale Semiconductor...
Page 603: ...Flash Memory MPC5566 Microcontroller Reference Manual Rev 2 13 38 Freescale Semiconductor...
Page 609: ...SRAM MPC5566 Microcontroller Reference Manual Rev 2 14 6 Freescale Semiconductor...
Page 1073: ...MPC5566 Microcontroller Reference Manual Rev 2 22 36 Freescale Semiconductor...
Page 1185: ...Nexus MPC5566 Microcontroller Reference Manual Rev 2 25 92 Freescale Semiconductor...