NXP Semiconductors MPC5566, Reference Manual

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Enhanced Direct Memory Access (eDMA)
MPC5566 Microcontroller Reference Manual, Rev. 2
9-10 Freescale Semiconductor
9.2.2.2 eDMA Error Status Register (EDMA_ESR)
The EDMA_ESR provides information concerning the last recorded channel error. Channel errors can be
caused by a configuration error (an illegal setting in the transfer control descriptor or an illegal priority
register setting in fixed arbitration mode) or an error termination to a bus master read or write cycle.
A configuration error is caused when the starting source or destination address, source or destination
offsets, minor loop byte count, and the transfer size represent an inconsistent state. The addresses and
offsets must be aligned on 0-modulo-transfer_size boundaries, and the minor loop byte count must be a
multiple of the source and destination transfer sizes. All source reads and destination writes must be
configured to the natural boundary of the programmed transfer size respectively.
In fixed arbitration mode, a configuration error is caused by any two channel priorities being equal within
a group, or any group priority levels being equal among the groups. For either type of priority
configuration error, the ERRCHN field is undefined. All channel priority levels within a group must be
unique and all group priority levels among the groups must be unique when fixed arbitration mode is
enabled.
If a scatter/gather operation is enabled upon channel completion, a configuration error is reported if the
scatter/gather address (DLAST_SGA) is not aligned on a 32-byte boundary. If minor loop channel linking
is enabled upon channel completion, a configuration error is reported when the link is attempted if the
TCD.CITER.E_LINK bit does not equal the TCD.BITER.E_LINK bit. All configuration error conditions
except scatter/gather and minor loop link error are reported as the channel is activated and assert an error
interrupt request if enabled. When properly enabled, a scatter/gather configuration error is reported when
the scatter/gather operation begins at major loop completion. A minor loop channel link configuration
error is reported when the link operation is serviced at minor loop completion.
If a system bus read or write is terminated with an error, the data transfer is immediately stopped and the
appropriate bus error flag is set. In this case, the state of the channel’s transfer control descriptor is updated
22–23
GRP0PRI
Channel group 0 priority. Group 0 priority level when fixed-priority group arbitration is enabled.
24–27 Reserved
28
ERGA
Enable round-robin group arbitration.
0 Fixed-priority arbitration is used for selection among the groups.
1 Round-robin arbitration is used for selection among the groups.
29
ERCA
Enable round-robin channel arbitration.
0 Fixed-priority arbitration is used for channel selection within each group.
1 Round-robin arbitration is used for channel selection within each group.
30
EDBG
Enable debug.
0 The assertion of the system debug control input is ignored.
1 The assertion of the system debug control input causes the eDMA to stall the start of a new channel.
Executing channels are allowed to complete. Channel execution resumes when either the system
debug control input is negated or the EDBG bit is cleared.
31 Reserved
Table 9-2. EDMA_CR Field Descriptions (continued)
Field Description