NXP Semiconductors MPC5566, Reference Manual

Page: 506 / 1268

External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 12-19
The following table describes the fields in the EBI calibration base register:
Table 12-10. EBI_BR n and EBI_CAL_BR n Field Descriptions
Field Description
0–16
BA
[0:16]
Base address. Compared to the corresponding unmasked address signals among ADDR[0:16] of the internal
address bus to determine if a memory bank controlled by the memory controller is being accessed by an internal
bus master.
Note: The upper three bits of the base address (BA) field, EBI_BR n [0:2], and EBI_CAL_BR n [0:2], are tied to a fixed
value of 001. These bits reset to their fixed value.
17–19 Reserved.
20
PS
Port size. Determines the data bus width of transactions to this chip select bank.
1
0 32-bit port
1 16-bit port
Note: The calibration port size must be 16-bits wide.
1
In the case where EBI_MCR[DBM] is set for 16-bit data bus mode, the PS bit value is forced to one (16-bit port) and the actual
value is ignored.
21–24 Reserved.
25
BL
Burst length. Determines the amount of data transferred in a burst for this chip select, measured in 32-bit words. The
number of beats in a burst is automatically determined by the EBI to be 4, 8, or 16 according to the port size so that
the burst fetches the number of words chosen by BL.
0 8-word burst length
1 4-word burst length
26
WEBS
Write enable/byte select. Controls the functionality of the WE/BE signals.
0 The WE/BE signals function as write enable (WE).
1 The WE/BE signals function as byte enable (BE).
Note: The 416-pin package implements WE/BE[0:3]
Note:
27
TBDIP
Toggle burst data in progress. Determines how long the BDIP signal is asserted for each data beat in a burst cycle.
See
Section 12.4.2.5.1, “TBDIP Effect on Burst Transfer ,” for details.
0 Assert BDIP throughout the burst cycle, regardless of wait state configuration.
1 Only assert BDIP (BSCY + 1) external bus cycles before expecting subsequent burst data beats.
28–29 Reserved.
30
BI
Burst inhibit. Determines whether or not burst read accesses are allowed for this chip select bank.
0 Enable burst accesses for this bank.
1 Disable burst accesses for this bank. This is the default value out of reset.
31
V
Valid bit. Indicates that the contents of this base register and option register pair are valid. The CS signal does not
assert unless its V-bit is set.
0 This bank is not valid.
1 This bank is valid.