NXP Semiconductors MPC5566, Reference Manual

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Enhanced Direct Memory Access (eDMA)
MPC5566 Microcontroller Reference Manual, Rev. 2
9-20 Freescale Semiconductor
9.2.2.14 eDMA Error Registers (EDMA_ERH, EDMA_ERL)
The EDMA_ERH and EDMA_ERL provide a bit map for the 64channels signaling the presence of an
error for each channel. EDMA_ERH supports channels 63–32, while EDMA_ERL covers channels 31–0.
The eDMA engine signals the occurrence of a error condition by setting the appropriate bit in this register.
The outputs of this register are enabled by the contents of the EDMA_EEIR, then logically summed across
groups of 16, 32, and 64 channels to form several group error interrupt requests which is then routed to the
interrupt controller. During the execution of the interrupt service routine associated with any DMA errors,
it is software’s responsibility to clear the appropriate bit, negating the error interrupt request. Typically, a
write to the EDMA_CER in the interrupt service routine is used for this purpose. Recall the normal DMA
Address: Base + 0x0020 Access: User R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
INT
63
INT
62
INT
61
INT
60
INT
59
INT
58
INT
57
INT
56
INT
55
INT
54
INT
53
INT
52
INT
51
INT
50
INT
49
INT
48
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
INT
47
INT
46
INT
45
INT
44
INT
43
INT
42
INT
41
INT
40
INT
39
INT
38
INT
37
INT
36
INT
35
INT
34
INT
33
INT
32
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 9-16. eDMA Interrupt Request High Register (EDMA_IRQRH)
Address: Base + 0x0024 Access: User R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
INT
31
INT
30
INT
29
INT
28
INT
27
INT
26
INT
25
INT
24
INT
23
INT
22
INT
21
INT
20
INT
19
INT
18
INT
17
INT
16
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
INT
15
INT
14
INT
13
INT
12
INT
11
INT
10
INT
09
INT
08
INT
07
INT
06
INT
05
INT
04
INT
03
INT
02
INT
01
INT
00
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 9-17. eDMA Interrupt Request Low Register (EDMA_IRQRL)
Table 9-14. EDMA_IRQRH, EDMA_IRQRL Field Descriptions
Field Description
0–63
INT
n
eDMA interrupt request n.
0 The interrupt request for channel n is cleared.
1 The interrupt request for channel n is active.