Fast Ethernet Controller (FEC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
15-17
causes the control logic to shift the data in the MMFR register out following a preamble generated by the
control state machine. Do not read the MMFR register during this time, because the contents is altered and
serially shifted, therefore this data can be invalid. Once the write management frame operation is complete,
the MII interrupt is generated. At this time the contents of the MMFR register matches the original value
written.
To generate an MII management interface read frame (read a PHY register) you must write
{01 10 PHYAD REGAD 10 XXXX} to the MMFR register (the content of the DATA field is ignored).
Writing this pattern causes the control logic to shift the data in the MMFR register out following a
preamble generated by the control state machine. Do not read the MMFR register during this time, because
the contents are altered and serially shifted, and can contain invalid data. Once the read management frame
operation is complete, the MII interrupt is generated. At this time the contents of the MMFR register
matches the original value written except for the DATA field contents that are replaced by the value read
from the PHY register.
If the MMFR register is written while frame generation is in progress, the frame contents is altered.
Software must poll the EIR[MII] bit or use the EIR[MII] bit to generate an interrupt to avoid writing to the
MMFR register while frame generation is in progress.
15.3.4.2.7
MII Speed Control Register (MSCR)
The MSCR provides control of the MII clock (FEC_MDC signal) frequency, allows a preamble drop on
the MII management frame, and provides observability (intended for manufacturing test) of an internal
counter used in generating the FEC_MDC clock signal.
describes the fields and functions of the MII speed control register (MSCR):
Address: Base + 0x0044
Access: User R/W
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
0
0
0
0
0
0
0
DIS_PRE
AMBLE
MII_SPEED
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 15-9. MII Speed Control Register (MSCR)
Table 15-10. MSCR Field Descriptions
Field
Description
0–23
Reserved, must be cleared.
24
DIS_PREAMBLE
Asserting this bit causes preamble (32 1’s) not to be prepended to the MII management frame. The MII
standard allows the preamble to be dropped if the attached PHY devices does not require it.
Summary of Contents for MPC5566
Page 81: ...Introduction MPC5566 Microcontroller Reference Manual Rev 2 1 24 Freescale Semiconductor...
Page 135: ...Signal Description MPC5566 Microcontroller Reference Manual Rev 2 2 54 Freescale Semiconductor...
Page 189: ...Reset MPC5566 Microcontroller Reference Manual Rev 2 4 20 Freescale Semiconductor...
Page 603: ...Flash Memory MPC5566 Microcontroller Reference Manual Rev 2 13 38 Freescale Semiconductor...
Page 609: ...SRAM MPC5566 Microcontroller Reference Manual Rev 2 14 6 Freescale Semiconductor...
Page 1073: ...MPC5566 Microcontroller Reference Manual Rev 2 22 36 Freescale Semiconductor...
Page 1185: ...Nexus MPC5566 Microcontroller Reference Manual Rev 2 25 92 Freescale Semiconductor...
