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398
Allocations for the CPU Unit
Section 7-3
n+1
IW0301
00-15
Teaching Axis Set-
ting 1-16
0: Nil
1: Specifies axis as teaching object
↑
: Nil
↓
: Nil
n+2
IW0302
00-15
Teaching Axis Set-
ting 17-32
0: Nil
1: Specifies axis as teaching object
↑
: Nil
↓
: Nil
Reserved
n+3
IW0320
00
Reserved
Reserved
01
Reserved
Reserved
02
Reserved
Reserved
03-15
Reserved
Reserved
Motion task 1
Control bit
n+4
IW0340
00
Motion Task Alarm
Reset
0: Nil
1: Does not turn ON the bit [Motion Task Alarm]
↑
: Clears the alarm occurring on motion task level
↓
: Nil
01
Motion Program
Start
0: Nil
1: Nil
↑
: Starts the motion program operation following
the specified Start Mode?
↓
: Nil
02-03
Start Mode
0, 3: Reads the program number and executes it
from top.
1: Executes the program from the block indicated
by Executing Motion Block Number. Operation at
resuming interrupted programs varies depending
on the command used or stopping status. For
details, see
7-4-3 Motion Task Control Bits
(page 443).
2: Executes program continuously from the next
block of the one indicated by Executing Motion
Block Number.
04
Deceleration Stop
0: Nil
1: Prohibits motion program start
↑
: Executes deceleration stop regardless of block
↓
: Nil
05
Block Stop
0: Nil
1: Prohibits motion program start?
↑
: Executes deceleration stop at the end of the
block currently being executed
↓
: Nil
06
Single-block Opera-
tion Mode
0: Single-block operation mode OFF
1: Single-block operation mode ON
↑
: Nil
↓
: Nil
07
Task Override
Enable
0: Disables task override value (override 100% is
used)
1: Enables task override value
↑
: Nil
↓
: Nil
08-15
Reserved
Reserved
Motion task 2
Control bit
n+5
IW0341
00-15
Same as for Motion
Task 1
Same as for Motion Task 1
Classification
Word
Variable
bit
Name
Specifications
Содержание CS1W-MCH71 -
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