NEC SV8500, Manual

Page: 2853 / 3438

VOL.3-366
CHAPTER 3 NETWORK INTERFACE
PLO Pin Assignments for Receiving or Distributing Clock
LT 10
LT 7
LT 6
LT 11 / PL 0
LT 3
LT 2
LBUS 1
LBUS 0
LT 5
LT 4
LT 1
LT 0
LT 8
LT 9
Phase Lock Oscillator (PLO)
PIR 0
• PLO connector Pin assignment
When the clock is distributed from a digital interface, use one pair of the “DIUxxx” leads among a maximum
of four inputs. The DIU leads have the following precedence: DIU0xx(High)-> DIU3xx(Low). When the
clock is received from an external high-stability oscillator, use the “DCSxx” leads.
The TSW (PH-SW10-A) circuit card includes Phase Lock Oscillator (PLO) functionality. The PLO input leads
appear on the connector shown below, on PIR 0 backplane.
PIN
No.
26
27
28
29
30
31
32
33
LEAD
NAME
DCSB0
DIU0B0
DIU1B0
DIU2B0
DIU3B0
SYN0B0
SYN1B0
LEAD
NAME
DCSA0
DIU0A0
DIU1A0
DIU2A0
DIU3A0
SYN0A0
SYN1A0
PIN
No.
1
2
3
4
5
6
7
8
PIN
No.
26
27
28
29
30
31
32
33
LEAD
NAME
DCSB0
DIU0B0
DIU1B0
DIU2B0
DIU3B0
SYN0B0
SYN1B0
LEAD
NAME
DCSA0
DIU0A0
DIU1A0
DIU2A0
DIU3A0
SYN0A0
SYN1A0
PIN
No.
1
2
3
4
5
6
7
8
40
41
42
43
44
45
46
47
48
49
50 15
16
17
18
19
20
21
22
23
24
25
DCSB1
DIU0B1
DIU1B1
DIU2B1
DIU3B1
SYN0B1
SYN1B1
DCSA1
DIU0A1
DIU1A1
DIU2A1
DIU3A1
SYN0A1
SYN1A1
40
41
42
43
44
45
46
47
48
49
50 15
16
17
18
19
20
21
22
23
24
25
DCSB1
DIU0B1
DIU1B1
DIU2B1
DIU3B1
SYN0B1
SYN1B1
DCSA1
DIU0A1
DIU1A1
DIU2A1
DIU3A1
SYN0A1
SYN1A1
for PLO
equipped
with TSW #0
with TSW #0
for PLO
equipped
with TSW #1
for PLO
equipped
with TSW #1
for receiving clock from
a High-Stability Oscillator
for distributing clock from
a digital interface
PLO Connector
for PLO
equipped
PLO Connector