Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Serial Communication Interface (eSCI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 20-9
NOTES
In 8-bit data format, only bits 8–15 of ESCI x _DR need to be accessed.
When transmitting in 9-bit data format and using 8-bit write instructions,
write first to ESCI
x _DR[0–7], then ESCI x _DR[8–15]. For 9-bit
transmissions, a single write can also be used.
Do not use ESCI x _DR in LIN mode, writes to this register are blocked in
LIN mode.
Even if parity generation/checking is enabled via ESCIx_CR[PE], the parity
bit is not masked out.
20.3.3.4 eSCI Status Register (ESCI x _SR)
The ESCI x _SR indicates the current status. The status flags can be polled, and some can also be used to
generate interrupts. All bits in ESCI x _SR except for RAF are cleared by writing 1 to them.
Table 20-5. ESCI x _DR Field Description
Field Description
0
R8
Received bit 8. R8 is the ninth data bit received when the eSCI is configured for 9-bit data format (M = 1).
1
T8
Transmit bit 8. T8 is the ninth data bit transmitted when the eSCI is configured for 9-bit data format (M = 1).
Note: If the value of T8 is the same as in the previous transmission, T8 does not have to be rewritten.The same value
is transmitted until T8 is rewritten.
2–7 Reserved.
8–15
R7–R0
T7–T0
Received bits/transmit bits 7–0 for 9-bit or 8-bit formats. Bits 7–0 from SCI communication can be read from
ESCI
x _DR[8–15] (provided that SCI communication was successful). Writing to ESCI x _DR [8–15] provides bits 7–0
for SCI transmission.
Address: Base + 0x0008 Access: R/W1c
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R TDRE TC RDRF IDLE OR NF FE PF 0 0 0 BERR 0 0 0 RAF
W w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R RX
RDY
TX
RDY
LWAKE STO
PB
ERR
CERR
CK
ERR
FRC 0 0 0 0 0 0 0 OVFL
W w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 20-5. eSCI Status Register (ESCI x _SR)