Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Serial Communication Interface (eSCI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
20-20 Freescale Semiconductor
20.4.3 Baud Rate Generation
A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the
transmitter. The value, 1 to 8191, written to the SBR0–SBR12 bits determines the system clock divider.
The SBR bits are in the eSCI control register 1 (ESCI
x _CR1). The baud rate clock is synchronized with
the system clock and drives the receiver. The baud rate clock divided by 16 drives the transmitter. The
receiver has an acquisition rate of 16 samples per bit time.
Baud rate generation is subject to one source of error when integer division of the system clock does not
result in the exact target frequency.
Table 20-17 lists some examples of achieving target baud rates with a system clock frequency of 128 MHz.
Table 20-15. Example of 8-bit Data Formats
Start
Bit
Data
Bits
Address
Bits
Parity
Bits
Stop
Bit
1 8 0 0 1
1 7 0 1 1
1 7 1
1
1
The address bit identifies the frame as an address char-
acter. Refer to Section 20.4.5.6, “Receiver Wake-up .”
0 1
Table 20-16. Example of 9-Bit Data Formats
Start
Bit
Data
Bits
Address
Bits
Parity
Bits
Stop
Bit
1 9 0 0 1
1 8 0 1 1
1 8 1
1
1
The address bit identifies the frame as an address char-
acter. Refer to Section 20.4.5.6, “Receiver Wake-up .”
0 1
Table 20-17. Baud Rates (Example: System Clock = 128 MHz)
Bits
SBR[0:12]
Receiver
Clock (Hz)
Transmitter
Clock (Hz)
Target Baud
Rate
Error
(%)
0x0023 3,657,143 228,571 230,400 –0.79
0x0045 1,855,072 115,942 115,200 +0.64
0x008B 920,863 57,554 57,600 –0.01
0x00D0 615,385 38,462 38,400 +0.16
0x01A1 306,954 19,185 19,200 –0.08
SCI baud rate
System clock
16 ESCIx_CR1[SBR]
×
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