Freescale Semiconductor MPC5565, Reference Manual

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Nexus
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 24-79
NOTE
The WT bits ONLY enable data trace if the tm bits within the development
control register (DC) have not already been set to enable data trace.
24.14.2.3 Data Trace Control Register (DTC)
The data trace control register controls whether DTM Messages are restricted to reads, writes or both for
a user programmable address range. There are two data trace channels controlled by the DTC for the
NXDM module.
22–20
DTE
DTE - Data trace end control
000 Trigger disabled
001-100 Reserved
101 Use internal watchpoint #1 (BWA1 register)
110 Use internal watchpoint #2 (BWA2 register)
111 Reserved
19–0 Reserved, read as 0.
Access: R/W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
RWT1 RWT2
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RC1 RC2
0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 24-58. Data Trace Control Register (DTC)
Table 24-50. DTC Field Description
Bit Description
31–30
RWT1 Read/write trace 1
00 No trace messages generated
X1 Enable data read trace
1X Enable data write trace
29–28
RWT2 Read/write trace 2
00 No trace messages generated
X1 Enable data read trace
1X Enable data write trace
27–8 Reserved, read as 0.
7
RC1
Range control 1
0 Condition trace on address within range (endpoints inclusive)
1 Condition trace on address outside of range (endpoints exclusive)
6
RC2
Range control 2
0 Condition trace on address within range (endpoints inclusive)
1 Condition trace on address outside of range (endpoints exclusive)
5–0 Reserved, read as 0.
Table 24-49. WT Field Description (continued)
Field Description