Freescale Semiconductor MPC5565, Reference Manual

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External Bus Interface (EBI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 12-19
26
WEBS
Write enable/byte select. Controls the functionality of the WE/BE[0:3] signals.
0 The WE/BE[0:3] signals function as WE[0:3].
1 The WE/BE[0:3] signals function as BE[0:3].
Note: 324-pin packages only implement WE/BE[0:1]
27
TBDIP
Toggle burst data in progress. Determines how long the BDIP signal is asserted for each data beat in a burst cycle.
Refer to
Section 12.4.2.5.1, “TBDIP Effect on Burst Transfer ,” for details.
0 Assert BDIP throughout the burst cycle, regardless of wait state configuration.
1 Only assert BDIP (BSCY + 1) external bus cycles before expecting subsequent burst data beats.
28–29 Reserved.
30
BI
Burst inhibit. Determines whether or not burst read accesses are allowed for this chip select bank.
0 Enable burst accesses for this bank.
1 Disable burst accesses for this bank. This is the default value out of reset.
31
V
Valid bit. Indicates that the contents of this base register and option register pair are valid. The appropriate CS signal
does not assert unless the corresponding V-bit is set.
0 This bank is not valid.
1 This bank is valid.
1
In the case where EBI_MCR[DBM] is set for 16-bit data bus mode, the PS bit value is ignored and is always treated as a 1
(16-bit port).
Table 12-10. EBI_BR n and EBI_CAL_BR n Field Descriptions (continued)
Field Description