Freescale Semiconductor MPC5565, Reference Manual

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External Bus Interface (EBI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 12-17
12.3.1.5 EBI Bus Monitor Control Register (EBI_BMCR)
The EBI_BMCR controls the timeout period of the bus monitor and whether it is enabled or disabled.
The following table describes the fields in the EBI bus monitor control register:
Base + 0x000C Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
BMT BME
0 0 0 0 0 0 0
W
Reset 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
Figure 12-4. EBI Bus Monitor Control Register (EBI_BMCR)
Table 12-9. EBI_BMCR Field Descriptions
Field Description
0–15 Reserved.
16–23
BMT[0:7]
Bus monitor timing. Defines the timeout period, in 8 external bus clock resolution, for the bus monitor. Refer to
Section 12.4.1.7, “Bus Monitor ,” for more details on bus monitor operation.
24
BME
Bus monitor enable. Controls whether the bus monitor is enabled for internal to external bus cycles. Regardless of
the BME value, the bus monitor is always disabled for chip select accesses, since these always use internal TA and
thus have no danger of hanging the system.
0 Disable bus monitor
1 Enable bus monitor (for non-chip select accesses only)
25–31 Reserved.
Timeout period
2 + (8 BMT)
×
External bus clock frequency
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