Freescale Semiconductor MPC5565, Reference Manual

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Flash Memory
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 13-25
• The read state is active when FLASH_MCR[PGM] = 1 and FLASH_MCR[PSUS] = 1 in the MCR.
(Program suspend).
• The read state is active when FLASH_MCR[ERS] = 1 and FLASH_MCR[ESUS] = 1 and
FLASH_MCR[PGM] = 0 in the MCR. (Erase suspend).
NOTE
Flash core reads are done through the BIU. In many cases the BIU does page
buffering to allow sequential reads to be done with higher performance. This
can create a data coherency issue that must be handled with software. Data
coherency can be an issue after a program or erase operation, as well as
shadow row operations.
In flash normal operating mode, registers can be written and the flash array can be written to do interlock
writes.
Reads attempted to invalid locations result in indeterminate data. Invalid locations occur when addressing
is done to blocks that do not exist in non 2
n
array sizes.
Interlock writes attempted to invalid locations (due to blocks that do not exist in non 2
n
array sizes), result
in an interlock occurring, but attempts to program or erase these blocks do not occur since they are forced
to be locked.
Refer to Section 13.3.2.2, “Low/Mid Address Space Block Locking Register (FLASH_LMLR) ,
Section 13.3.2.3, “High Address Space Block Locking Register (FLASH_HLR) ” and Section 13.3.2.4,
“Secondary Low/Mid Address Space Block Locking Register (FLASH_SLMLR) ” for more information.
13.4.2.2 Read While Write (RWW)
The flash core is divided into partitions. Partitions are always comprised of two or more blocks. Partitions
are used to determine read while write (RWW) groupings. While a write (program or erase) is being done
within a given partition, a read can be simultaneously executed to any other partition. Partitions are listed
in
Table 13-3 . Each partition in high address space comprises of two 128-KB blocks. Note that the shadow
block has unique RWW restrictions described in Section 13.4.2.5, “Flash Shadow Block .”
The flash core is also divided into blocks to implement independent erase or program protection. The
shadow block exists outside the normal address space and is programmed, erased and read independently
of the other blocks. The shadow block is included to support systems that require NVM for security or
system initialization information.
A software mechanism is provided to independently lock or unlock each block in high-, mid-, and
low-address space against program and erase.
13.4.2.3 Flash Programming
Programming changes the value stored in an array bit from logic 1 to logic 0 only. Programming cannot
change a stored logic 0 to a logic 1. Addresses in locked/disabled blocks cannot be programmed. The user
can program the values in any or all of eight words within a page in a single program sequence. Word
addresses are selected using bits 4:2 of the page-bound word.