Freescale Semiconductor MPC5565, Reference Manual

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Preface
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 21-11
7
FRZACK
Freeze mode acknowledge. Indicates that FlexCAN2 is in freeze mode and its prescaler is stopped. The
freeze mode request cannot be granted until current transmission and reception processes have finished.
Therefore the software can poll the FRZACK bit to know when FlexCAN2 has actually entered freeze mode.
If freeze mode request is negated, then this bit is negated after the FlexCAN2 prescaler is running again. If
freeze mode is requested while FlexCAN2 is disabled, then the FRZACK bit will only be set when the low
power mode is exited. Refer to
Section 21.4.6.1, “Freeze Mode ,” for more information.
0 FlexCAN2 not in freeze mode, prescaler running
1 FlexCAN2 in freeze mode, prescaler stopped
8–9 Reserved.
10
WRNEN
Warning interrupt enable. When asserted, this bit enables the generation of the TWRNINT and RWRNINT
flags in the Error and Status Register. If WRNEN is negated, the TWRNINT and RWRNINT flags will always
be 0, independent of the values of the error counters, and no warning interrupt will ever be generated.
1 = TWRNINT and RWRNINT bits are set when the respective error counter transition from <96
to
≥
96.
0 = TWRNINT and RWRNINT bits are zero, independent of the values in the error counters.
11
MDISACK
Low power mode acknowledge. Indicates whether FlexCAN2 is disabled. This cannot be performed until all
current transmission and reception processes have finished, so the CPU can poll the MDISACK bit to know
when FlexCAN2 has actually been disabled. Refer to
Section 21.4.6.2, “Module Disabled Mode ,” for more
information.
0 FlexCAN2 not disabled
1 FlexCAN2 is disabled
12-13 Reserved.
14
SRXDIS
This bit defines whether FlexCAN is allowed to receive frames transmitted by itself. If this bit is
asserted, frames transmitted by the module will not be stored in any MB, regardless if the MB is
programmed with an ID that matches the transmitted frame, and no interrupt flag or interrupt signal
will be generated due to the frame reception.
1 = Self reception disabled
0 = Self reception enabled
15
MBFEN
Message buffer filter enable. This bit provides the capability of enabling either individual masking of every
message buffer, or global masking of message buffers.
By negating MBFEN, the global masking capability is enabled in which FlexCAN uses the Rx ID masking
scheme of RXGMASK, RX14MASK and RX15MASK. In this scheme, MB14 and MB15 have individual
masks and the others share the global mask. The scheme does not provide a reception queue; i.e. a received
message will always fill the first matching buffer, setting the CODE field to overrun if the buffer contained an
unread message. Refer to
Section 21.3.3.4, “RX Mask Registers ” for more information. This global masking
scheme is compatible with previous FlexCAN versions and at reset MBFEN is negated so that existing
software retains compatibility.
By asserting MBFEN, individual Rx ID masking and the reception queue features are enabled. In this
scheme, individual receive mask registers (RXIM[0-63]) are provided for each MB. Upon receiving a
message, FlexCAN will look in the reception queue for the first empty matching MB. Refer to
Section 21.3.3.5, “RX Individual Mask Registers (CANx_RXIMR0 – CANx_RXIMR63) ” and Section 21.4.3.2,
“Reception Queue ” for more information.
0 Individual RX masking and reception queue features are disabled (thus the device is compatible with
previous FlexCAN versions, i.e. one global mask register is used).
1 Individual RX masking and reception queue features are enabled.
Table 21-7. CAN x _MCR Field Descriptions (continued)
Field Description