Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Direct Memory Access (eDMA)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 9-29
count is exhausted, additional processing is performed, including the final address pointer
updates, reloading the TCDn.CITER field, and a possible fetch of the next TCD
n from memory
as part of a scatter/gather operation.
— Data path: This module implements the actual bus master read/write datapath. It includes 32
bytes of register storage (matching the maximum transfer size) and the necessary mux logic to
support any required data alignment. The system read data bus is the primary input, and the
system write data bus is the primary output.
The address and data path modules directly support the 2-stage pipelined system bus. The
address path module represents the 1st stage of the bus pipeline (the address phase), while the
data path module implements the 2nd stage of the pipeline (the data phase).
— Program model/channel arbitration: This module implements the first section of eDMA’s
programming model as well as the channel arbitration logic. The programming model registers
are connected to the slave bus (not shown). The eDMA peripheral request inputs and eDMA
interrupt request outputs are also connected to this module (via the Control logic).
— Control: This module provides all the control functions for the eDMA engine. For data
transfers where the source and destination sizes are equal, the eDMA engine performs a series
of source read, destination write operations until the number of bytes specified in the inner
‘minor loop’ byte count has been moved.
A minor loop interaction is defined as the number of bytes to transfer ( n bytes) divided by the
transfer size. Transfer size is defined as the following:
if (SSIZE < DSIZE)
transfer size = destination transfer size (# of bytes)
else
transfer size = source transfer size (# of bytes)
Minor loop TCD variables are SOFF, SMOD, DOFF, DMOD, NBYTES, SADDR, DADDR,
BWC, ACTIVE, AND START. Major loop TCD variables are DLAST, SLAST, CITER,
BITER, DONE, D_REQ, INT_MAJ, MAJOR_LNKCH, and INT_HALF.
For descriptors where the sizes are not equal, multiple access of the smaller size data are
required for each reference of the larger size. As an example, if the source size references 16-bit
data and the destination is 32-bit data, two reads are performed, then one 32-bit write.
• TCD local memory
— Memory controller: This logic implements the required dual-ported controller, handling
accesses from both the eDMA engine as well as references from the slave bus. As noted earlier,
in the event of simultaneous accesses, the eDMA engine is given priority and the slave
transaction is stalled. The hooks to a BIST controller for the local TCD memory are included
in this module.
— Memory array: The TCD is implemented using a single-ported, synchronous compiled RAM
memory array.