Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Serial Communication Interface (eSCI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
20-4 Freescale Semiconductor
20.3.3 Register Descriptions
This section contains the register descriptions in address order. Each description includes a standard
register diagram with an associated figure number. Details of register bit and field functions follow the
register diagrams, in bit order.
20.3.3.1 eSCI Control Register 1 (ESCI x _CR1)
Table 20-2. Module Memory Map
Address Register Name Register Description Bits
Base
0xFFFB_0000 (A)
0xFFFB_4000 (B) ESCI x _CR1 eSCI control register 1 32
Base + 0x0004 ESCI x _CR2 eSCI control register 2 16
Base + 0x0006 ESCI x _DR eSCI data register 16
Base + 0x0008 ESCI x _SR eSCI status register 32
Base + 0x000C ESCI x _LCR LIN control register 32
Base + 0x0010 ESCI x _LTR LIN transmit register 32
Base + 0x0014 ESCI x _LRR LIN receive register 32
Base + 0x0018 ESCI x _LPR LIN cyclic redundancy check polynomial register 32
Address: Base + 0x0000 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0
SBR
0
SBR
1
SBR
2
SBR
3
SBR
4
SBR
5
SBR
6
SBR
7
SBR
8
SBR
9
SBR
10
SBR
11
SBR
12
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
LOOPS
0
RSRC M WAKE ILT PE PT TIE TCIE RIE ILIE TE RE RWU SBK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 20-2. eSCI Control Register 1 (ESCI x _CR1)