Freescale Semiconductor MPC5565, Reference Manual

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System Integration Unit (SIU)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
6-118 Freescale Semiconductor
Refer to Section 6.3.1.153, “eQADC Trigger Input Select Register (SIU_ETISR) ” for the
SIU_ETISR[TSEL0]–SIU_ETISR[TSEL5] bit definitions.
6.4.5.2 SIU External Interrupt Input Multiplexing
The sixteen SIU external interrupt inputs can be connected to either an external pin or to serialized output
signals from a DSPI module. The input source for each SIU external interrupt is individually specified in
the external IRQ input select register (SIU_EIISR).
As shown in the figure, the IRQ[0] input of the SIU can be connected to either the IRQ[0]_GPIO[203] pin,
the PCSB[0] serial input signal, the PCSC[1] deserialized output signal, or the PCSD[2] deserialized
output signal. The remaining IRQ inputs are multiplexed in the same manner. The inputs to the IRQ from
each DSPI module are offset by one so that if more than one DSPI module is connected to the same
external device type, a separate interrupt can be generated for each device. This also applies to DSPI
modules connected to external devices of different type that have status bits in the same bit location of the
deserialized information.
An example of the multiplexing of an SIU external interrupt input is given in Figure 6-161 .
Figure 6-161. DSPI Serialized Input Multiplexing
6.4.5.3 Multiplexed Inputs for DSPI Multiple Transfer Operation
Each DSPI module can be combined in a serial or parallel chain (multiple transfer operation). Serial
chaining allows SPI operation with an external device that has more bits than one DSPI module.
In a serial chain, one DSPI module operates as a master, the second, third, or fourth DSPI modules operate
as slaves. The data output (SOUT) of the master is connected to the data input (SIN) of the slave. The
SOUT of a slave is connected to the SIN of subsequent slaves until the last module in the chain, where the
SOUT is connected to an external pin, which connects to the input of an external SPI device. The slave
DSPI and external SPI device use the master peripheral chip select (PCS) and clock (SCK). The trigger
input of the master allows a slave DSPI to trigger a transfer when a data change occurs in the slave DSPI
and the slave DSPI is operating in change in data mode. The trigger input of the master is connected to the
MTRIG output of the slave. If more than two DSPIs are chained in change in data mode, a chain must be
connected of MTRIG outputs to trigger inputs through the slaves with the last slave MTRIG output
connected to the master trigger input.
An example of a serial chain is shown in Figure 6-162 .
.
IRQ[0]
IRQ[0]_GPIO[203]
DSPI B[0] serialized input
DSPI C[1] serialized input
DSPI D[2] serialized input
ESEL[0]
ESEL[1]