Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 18-113
Step Three: Configure the eQADC control registers.
1. Configure Section 18.3.2.7, “eQADC Interrupt and eDMA Control Registers 0–5
(EQADC_IDCRn) .”
a) Set EOQIE1 to enable the End of Queue Interrupt request.
b) Set CFFS1 and RFDS3 to configure the eQADC to generate eDMA requests to push commands
into CFIFO1 and to pop result data from RFIF03.
c) Set CFINV1 to invalidate the contents of CFIFO1.
d) Set RFDE3 and CFFE1 to enable the eQADC to generate eDMA requests. Command transfers
from the RAM to the CFIFO1 starts immediately.
e) Set RFOIE3 to indicate if RFIFO3 overflows.
f) Set CFUIE1 to indicate if CFIFO1 underflows.
2. Configure MODE1 to continuous-scan rising edge external trigger mode in Section 18.3.2.6,
“eQADC CFIFO Control Registers 0–5 (EQADC_CFCRn) .”
Step Four: Command transfer to ADCs and result data reception.
When an external rising edge event occurs for CFIFO1, the eQADC automatically begins
transferring commands from CFIFO1 when it becomes the highest priority CFIFO trying to send
commands to ADC1. The received results are placed in RFIFO3 and then moved to result queue 1
by the eDMA.
18.5.2 eQADC/eDMA Controller Interface
This section provides an overview of the eQADC/eDMA interface and general guidelines about how the
eDMA should be configured in order for it to correctly transfer data between the queues in system memory
and the eQADC FIFOs.
18.5.2.1 Command Queue/CFIFO Transfers
In transfers involving command queues and CFIFOs, the eDMA moves data from a queued source to a
single destination as shown in
Figure 18-65 .
Figure 18-65. Command Queue/CFIFO Interface
Command 1
Command 2
Command 3
•
Command n-1
Command n
One command transfer
per DMA request
CFPRx
Source Address
Destination Address
CFIFO Push Register
•
•
••
•
eDMA_TCD n