Freescale Semiconductor MPC5565, Reference Manual

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IEEE 1149.1 Test Access Port Controller (JTAGC)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
23-10 Freescale Semiconductor
23.4.4.5 HIGHZ Instruction
HIGHZ selects the bypass register as the shift path between TDI and TDO. While HIGHZ is active, all
output drivers are placed in an inactive drive state (for example, high impedance). HIGHZ also asserts the
internal system reset for the MCU to force a predictable internal state.
23.4.4.6 IDCODE Instruction
IDCODE selects the 32-bit device identification register as the shift path between TDI and TDO. This
instruction allows interrogation of the MCU to determine its version number and other part identification
data. IDCODE is the instruction placed into the instruction register when the JTAGC is reset.
23.4.4.7 SAMPLE Instruction
The SAMPLE instruction obtains a sample of the system data and control signals present at the MCU input
pins and just before the boundary scan register cells at the output pins. This sampling occurs on the rising
edge of TCK in the capture-DR state when the SAMPLE instruction is active. The sampled data is viewed
by shifting it through the boundary scan register to the TDO output during the Shift-DR state. There is no
defined action in the update-DR state. Both the data capture and the shift operation are transparent to
system operation.
23.4.4.8 SAMPLE/PRELOAD Instruction
The SAMPLE/PRELOAD instruction has two functions:
• The SAMPLE part of the instruction samples the system data and control signals on the MCU input
pins and just before the boundary scan register cells at the output pins. This sampling occurs on the
rising-edge of TCK in the capture-DR state when the SAMPLE/PRELOAD instruction is active.
The sampled data is viewed by shifting it through the boundary scan register to the TDO output
during the shift-DR state. Both the data capture and the shift operation are transparent to system
operation.
• The PRELOAD part of the instruction initializes the boundary scan register cells before selecting
the EXTEST or CLAMP instructions to perform boundary scan tests. This is achieved by shifting
in initialization data to the boundary scan register during the shift-DR state. The initialization data
is transferred to the parallel outputs of the boundary scan register cells on the falling edge of TCK
in the update-DR state. The data is applied to the external output pins by the EXTEST or CLAMP
instruction. System operation is not affected.
23.4.5 Boundary Scan
The boundary scan technique allows signals at component boundaries to be controlled and observed
through the shift-register stage associated with each pad. Each stage is part of a larger boundary scan
register cell, and cells for each pad are interconnected serially to form a shift-register chain around the
border of the design. The boundary scan register consists of this shift-register chain, and is connected
between TDI and TDO when the EXTEST, SAMPLE, or SAMPLE/PRELOAD instructions are loaded.
The shift-register chain contains a serial input and serial output, as well as clock and control signals.