Freescale Semiconductor MPC5565, Reference Manual

Page: 56 / 1153

Introduction
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 1-21
1.6 Multi-Master Operation Memory Map
NOTE
When multi-master mode is enabled, the bus is permanently granted to the
external master; therefore, the MPC5565 MCU cannot be a master on a
multi-master bus, only a slave.
When the MCU acts as a slave in a multi-master system, the external bus interface (EBI) translates the
24-bit external address to a 32-bit internal address.
Table 1-4 lists the translation parameters.
Table 1-5 shows the memory map for the MCU acting as a slave in a multi-master system from the point
of view of the external master.
Table 1-4. External to Internal Memory Map Translation Table for Slave Mode
Ext Addr[8:11]
1
1
Only the lower 24 address signals (ADDR[8:31]) are available off-chip for external master accesses.
Internal Address[0:11] Bytes Internal Slave Internal Address Range
0b0xxx N/A 8 MB N/A n/a. Off-chip flash access
0b10xx 0b0000_0000_00xx 4 MB Internal flash array 0x0000_0000–0x003F_FFFF
0b1100 0b0100_0000_0000 1 MB Internal SRAM 0x4000_0000–0x4000_FFFF
0b1101 0b0110_0000_0000 1 MB Reserved
2
2
Reserved for a future module that requires its own crossbar slave port.
0x6000_0000–0x600F_FFFF
0b1110 0b1100_0011_1111 1 MB Bridge A peripherals 0xC3F0_0000–0xC3FF_FFFF
0b1111 0b1111_1111_1111 1 MB Bridge B peripherals 0xFFF0_0000–0xFFFF_FFFF
Table 1-5. MPC5565 Family Slave Memory Map as Seen from an External Master
External Address Range
1
1
Only the lower 24 address signals (ADDR[8:31]) are available off-chip for external master accesses.
Size (bytes) Use
0x0000_0000
2
–0x007F_FFFF
2
This address range is not part of the MPC5500 family slave memory map, rather it is shown to illustrate the addressing
scheme for off-chip accesses in multi-master mode.
8 MB n/a. Used for off-chip memory accesses
0x0080_0000–0x009F_FFFF 2 MB Slave flash
3
3
The shadow row of the slave flash is not accessible by an external master.
0x00A0_0000–0x00BF_FFFF 2 MB Reserved
0x00C0_0000–0x00C1_3FFF 80 KB Slave internal SRAM
0x00C1_4000–0x00CF_FFFF 1 MB–80 KB (less total SRAM) Reserved
0x00D0_0000–0x00DF_FFFF 1 MB Reserved
0x00E0_0000–0x00EF_FFFF 1 MB Slave bridge A peripherals
0x00F0_0000–0x00FF_FFFF 1 MB Slave bridge B peripherals