Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Time Processing Unit (eTPU)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
17-24 Freescale Semiconductor
17.4.4 Time Base Registers
Time base registers allow the configuration and visibility of internally-generated time bases TCR1 and
TCR2. There is one of each of these registers for each eTPU engine.
NOTE
Writes to this register generate a bus error and are ineffective when
MDIS = 1. Reads are always permitted.
18–26 Reserved.
27–31
ETB
[0:4]
Entry table base. Determines the location of the microcode entry table for the eTPU functions in SCM. More
information about entry points is located in the
eTPU Reference Manual . The following table shows the entry table
base address options.
1
The time base registers can still be read in stop mode, but writes are ineffective and a bus error is issued. Global channel
registers and SDM can be accessed normally.
Table 17-10. ETPU_ECR Field Descriptions (continued)
Field Description
ETB
Entry Table Base
Address for CPU Host
Address (byte format)
Entry Table Base Address
for Microcode Address
(word format)
00000 0x0000_0000 0x0000_0000
00001 0x0000_0800 0x0000_0200
00010 0x0000_1000 0x0000_0400
.
.
.
. .
.
.
. .
.
.
.
11110 0x0000_F000 0x0000_3C00
11111 0x0000_F800 0x0000_3E00