Freescale Semiconductor MPC5565, Reference Manual

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System Integration Unit (SIU)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 6-23
6.3.1.12 Pad Configuration Registers (SIU_PCR)
The following subsections define pad configuration registers (PCR) in the SIU_PCR segment. These
registers define the pad configuration for all configurable device pins that specify that active function,
direction, and electrical attributes for the pin. The information presented pertains to which bits and fields
are active for a given pin or group of pins, and the reset state of the register.
The reset state of SIU_PCRs given in this section is the value before the BAM program executes. The
BAM program can change some pad configuration registers based on the reset configuration. Refer to the
BAM chapter for more detailed information.
The SIU_PCRs are 16-bit registers that are read from or written to as:
• 16-bit values aligned on 16-bit boundaries, or
• 32-bit values aligned on 32-bit address boundaries.
NOTE
The fields available in a SIU_PCR depend on the type of pad it controls.
Refer to the SIU_PCR definition.
All device pin names begin with the primary function, followed by the alternate function, and then GPIO.
In some cases, the third function can be a secondary alternate, which supersedes the GPIO. Those
exceptions are noted in the documentation. For example, SIU_PCR85 configures the
CNTXB_PCSC[3]_GPIO[85] muxed signal, where CNTXB is the primary function, PCSC[3] is the
alternate function. For identification of the source module for primary and alternate functions, and the
description of these signals, refer to
Chapter 2, “Signal Description ” of this manual. Refer to the chapter
for the specific module that uses the signal for an additional signal description.
Figure 6-13 shows a sample PCR register with all bit fields displayed:
Figure 6-13. Sample PCR Register Description
Address: Base + 0x0014 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0
PA
1
1
The PA fields in PCR0 through 3 and PCR4 through 7 must not be configured simultaneously to select ADDR[8:11] as an input.
Only one pin is to be configured to provide the address input.
OBE IBE DSC ODE HYS
2
2
If external master operation is enabled, clear the HYS bit to 0.
0 0
WPE WPS
W
RESET: 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1
SIU register address
Read values
Write values
Reset values
Access
Field
Bit
number
name
Footnotes
Register bit
range [3:5]
Field bit
range [0:2]
Permissions