Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 18-25
4
CFUF n
CFIFO underflow flag n . Indicates an underflow event on CFIFO n . CFUF n is set when CFIFO n is in the TRIGGERED
state and it becomes empty. No commands are transferred from an underflowing CFIFO, and command transfers
from lower priority CFIFOs are not blocked. When CFUIE
n (see Section Section 18.3.2.7, “eQADC Interrupt and
eDMA Control Registers 0–5 (EQADC_IDCRn) ”) and CFUF n are both asserted, the eQADC generates an interrupt
request.
Apart from generating an independent interrupt request for a CFIFO
n underflow event, the eQADC also provides a
combined interrupt at which the result FIFO overflow interrupt, the command FIFO underflow interrupt, and the
command FIFO trigger overrun interrupt requests of all CFIFOs are ORed. When RFOIE
n , CFUIE n , and TORIE n
are all asserted, this combined interrupt request is asserted whenever one of the following 18 flags becomes
asserted: RFOF
n , CFUF n , and TORF n (assuming that all interrupts are enabled). Refer to Section 18.4.7, “eQADC
eDMA/Interrupt Request ,” for details. Writing a 1 clears CFUF n . Writing a 0 has no effect.
0 No CFIFO underflow event occurred
1 A CFIFO underflow event occurred
5
SSS n
CFIFO single-scan status bit n . When asserted, enables the detection of trigger events for CFIFOs programmed into
single-scan level- or edge-trigger mode, and works as trigger for CFIFOs programmed into single-scan
software-trigger mode. Refer to
Section 18.4.3.5.2, “Single-Scan Mode ,” for further details. The SSS n bit is set by
writing a 1 to the SSE n bit (see Section Section 18.3.2.6, “eQADC CFIFO Control Registers 0–5
(EQADC_CFCRn) ”). The eQADC clears the SSS n bit when a command with an asserted EOQ bit is transferred from
a CFIFO in single-scan mode, when a CFIFO is in single-scan level trigger mode and its status changes from the
TRIGGERED state due to the detection of a closed gate, or when the value of the CFIFO operation mode MODE
n
(see Section 18.3.2.6, “eQADC CFIFO Control Registers 0–5 (EQADC_CFCRn) ”) is changed to disabled. Writing to
SSS n has no effect. SSS n has no effect in continuous-scan or in disabled mode.
0 CFIFO in single-scan, level-, or edge-trigger mode ignores trigger events, or CFIFO in single-scan software-trigger
mode is not triggered.
1 CFIFO in single-scan level- or edge-trigger mode detects a trigger event, or CFIFO in single-scan software-trigger
mode is triggered.
6
CFFF n
CFIFO fill flag n . CFFF n is set when the CFIFO n is not full. When CFFE n (see Section 18.3.2.7, “eQADC Interrupt
and eDMA Control Registers 0–5 (EQADC_IDCRn) ”) and CFFF n are both asserted, an interrupt or an eDMA request
is generated depending on the status of the CFFS n bit. When CFFS n is negated (interrupt requests selected),
software clears CFFF n by writing a 1 to it. Writing a 0 has no effect. When CFFS n is asserted (eDMA requests
selected), CFFF n is automatically cleared by the eQADC when the CFIFO becomes full.
0 CFIFO n is full.
1 CFIFO n is not full.
Note: When generation of interrupt requests is selected (CFFS n =0), CFFF n must only be cleared in the ISR after
the CFIFO n push register is accessed.
Note: CFFF n should not be cleared when CFFSn is asserted (eDMA requests selected).
7–11 Reserved.
Table 18-12. EQADC_FISR n Field Descriptions (continued)
Field Description