Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Serial Communication Interface (eSCI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 20-17
20.3.3.7 LIN Receive Register (ESCI x _LRR)
ESCI x _LRR can be ready only when ESCI x _SR[RXRDY] is set.
NOTE
Application software must ensure that ESCI x _LRR be read before new data
or checksum bytes or CRCs are received from the LIN bus.
Address: Base + 0x0014 Access: R/O
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 20-9. LIN Receive Register (ESCI x _LRR)
Table 20-13. ESCI x _LRR Field Descriptions
Field Description
0–7
D n
Data bit n . Provides received data bytes from RX frames. Data is only valid when the ESCI x _SR[RXRDY] flag is set.
CRC and checksum information are not available in the ESCI x _LRR unless they are treated as data. It is possible
to treat CRC and checksum bytes as data by deactivating the CSUM respectively CRC control bits in the ESCI x _LTR;
however, then CRC and CSUM checking has to be performed by software.
Data bytes must be read from the ESCI x _LRR (by CPU or DMA) before any new bytes (including CRC or checksum)
are received from the LIN bus otherwise the data byte is lost and OVFL is set.
Note: The data must be collected and the LIN frame finished (including CRC and checksum if applicable) before a
wake-up character can be sent.
8–31 Reserved.