Interrupt Controller (INTC)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor
10-5
In debug mode the interrupt controller operation is identical to its normal operation of software vector
mode or hardware vector mode.
10.1.4.1
Software Vector Mode
In software vector mode, there is a common interrupt exception handler address which is calculated by
hardware as shown in
. The upper half of the interrupt vector prefix register (IVPR) is added
to the offset contained in the external input interrupt vector offset register (IVOR4). Note that since bits
IVOR4[28:31] are not part of the offset value, the vector offset must be located on a quad-word (16-byte)
aligned location in memory.
In software vector mode, the interrupt exception handler software must read the INTC interrupt
acknowledge register (INTC_IACKR) to obtain the vector associated with the corresponding peripheral
or software interrupt request. The INTC_IACKR register contains a 32-bit address for a vector table base
address (VTBA) plus an offset to access the interrupt vector (INTVEC). The address is then used to branch
to the corresponding routine for that peripheral or software interrupt source.
Figure 10-5. Software Vector Mode: Interrupt Exception Handler Address Calculation
Reading the INTC_IACKR acknowledges the INTC’s interrupt request and negates the interrupt request
to the processor. The interrupt request to the processor does not clear if a higher priority interrupt request
arrives. Even in this case, INTVEC does not update to the higher priority request until the lower priority
interrupt request is acknowledged by reading the INTC_IACKR. The reading also pushes the PRI value
in the INTC current priority register (INTC_CPR) onto the LIFO and updates PRI in the INTC_CPR with
the priority of the interrupt request. The INTC_CPR masks any peripheral or software settable interrupt
request at the same or lower priority of the current value of the PRI field in INTC_CPR from generating
an interrupt request to the processor.
The interrupt exception handler must write to the end-of-interrupt register (INTC_EOIR) to complete the
operation. Writing to the INTC_EOIR ends the servicing of the interrupt request. The INTC’s LIFO is
popped into the INTC_CPR's PRI field by writing to the INTC_EOIR, and the size of a write does not
affect the operation of the write. Those values and sizes written to this register neither update the
INTC_EOIR contents nor affect whether the LIFO pops. For possible future compatibility, write four bytes
of all 0s to the INTC_EOIR. The timing relationship between popping the LIFO and disabling recognition
of external input has no restriction. The writes can happen in either order.
31
16
15
0
IVPR
31
28
27
16
15
0
+ IVOR4
31
28
27
16
15
0
0x00
0x00
OFFSET
OFFSET
PREFIX
0x0000
PREFIX
= Interrupt exception
0x0000
handler address
Summary of Contents for MPC5565
Page 18: ...MPC5565 Microcontroller Reference Manual Devices Supported MPC5565 MPC5565 RM Rev 1 0 09 2007...
Page 34: ...MPC5565 Reference Manual Rev 1 0 Freescale Semiconductor 15...
Page 35: ...MPC5565 Reference Manual Rev 1 0 16 Freescale Semiconductor...
Page 553: ...Flash Memory MPC5565 Microcontroller Reference Manual Rev 1 0 13 38 Freescale Semiconductor...
Page 559: ...SRAM MPC5565 Microcontroller Reference Manual Rev 1 0 14 6 Freescale Semiconductor...
Page 973: ...Preface MPC5565 Microcontroller Reference Manual Rev 1 0 21 36 Freescale Semiconductor...
Page 1153: ...Calibration MPC5565 Microcontroller Reference Manual Rev 1 0 B 8 Freescale Semiconductor...
