Enhanced Direct Memory Access (eDMA)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor
9-17
9.2.2.12
eDMA Clear DONE Status Bit Register (EDMA_CDSBR)
The EDMA_CDSBR provides a simple memory-mapped mechanism to clear the DONE bit in the TCD
of the given channel. The data value on a register write causes the DONE bit in the corresponding transfer
control descriptor to be cleared. Setting bit 1 (CDSB
n
) provides a global clear function, forcing all DONE
bits to be cleared.
9.2.2.13
eDMA Interrupt Request Register (EDMA_IRQRL)
The EDMA_IRQRL provide a bit map for the 32 channels signaling the presence of an interrupt request
for each channel. EDMA_IRQRL maps to channels 31–0.
The eDMA engine signals the occurrence of a programmed interrupt upon the completion of a data transfer
as defined in the transfer control descriptor by setting the appropriate bit in this register. The outputs of
this register are directly routed to the interrupt controller (INTC). During the execution of the interrupt
service routine associated with any given channel, it is software’s responsibility to clear the appropriate
bit, negating the interrupt request. Typically, a write to the EDMA_CIRQR in the interrupt service routine
is used for this purpose.
The state of any given channel’s interrupt request is directly affected by writes to this register; it is also
affected by writes to the EDMA_CIRQR. On writes to the EDMA_IRQRL, a 1 in any bit position clears
the corresponding channel’s interrupt request. A zero in any bit position has no affect on the corresponding
channel’s current interrupt status. The EDMA_CIRQR is provided so the interrupt request for a
single
channel can easily be cleared without the need to perform a read-modify-write sequence to the
EDMA_IRQRL.
Address: Base + 0x001F
Access:User W/O
0
1
2
3
4
5
6
7
R
0
0
0
0
0
0
0
0
W
CDSB[0:6]
Reset
0
0
0
0
0
0
0
0
Figure 9-13. eDMA Clear DONE Status Bit Register (EDMA_CDSBR)
Table 9-13. EDMA_CDSBR Field Descriptions
Field
Description
0
Reserved.
1–7
CDSB[0:6]
Clear DONE status bit.
0–31 Clear the corresponding channel’s DONE bit
32–63 Reserved
64–127 Clear all TCD DONE bits
Note:
Bit 2 (CDSB1) is not used.
Summary of Contents for MPC5565
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