Freescale Semiconductor MPC5565, Reference Manual

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External Bus Interface (EBI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
12-62 Freescale Semiconductor
12.5.3 Running with Asynchronous Memories
The EBI also supports asychronous memories. In this case, the CLKOUT, TS, and BDIP pins are not used
by the memory and bursting is not supported. However, the EBI still drives these outputs, and always
drives and latches all signals at positive edge CLKOUT (i.e., there is no asynchronous mode for the EBI).
The data timing is controlled by setting the SCY bits in the appropriate option register to the proper number
of wait states to work with the access time of the asynchronous memory, just as done for a synchronous
memory.
12.5.3.1 Example Wait State Calculation
This example applies to any chip select memory, synchronous or asynchronous.
As an example, say we have a memory with 50 ns access time, and we are running the external bus at
66 MHz (CLKOUT period: 15.2 ns). When the input data specification for the MCU is 4 ns:
Number of wait states = (access time) / (CLKOUT period) + (0 or 1) (depending on setup time)
50/15.2 = 3 with 4.4 ns remaining (so we need at least three wait states, now check setup time)
15.2 - 4.4 = 10.8 ns (this is the achieved input data setup time)
Because actual input setup (10.8 ns) is greater than the input setup specification (4.0 ns), three wait states
is sufficient. If the input setup is less than 4.0 ns, use four wait states.
12.5.3.2 Timing and Connections for Asynchronous Memories
The connections to an asynchronous memory are the same as for a synchronous memory, except that the
CLKOUT, TS, and BDIP signals are not used.
Figure 12-44 shows a block diagram of an MCU connected
to an asynchronous memory.