Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
18-24 Freescale Semiconductor
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PF n
Pause flag n . PF behavior changes according to the CFIFO trigger mode.
• In edge trigger mode, PF n is set when the eQADC completes the transfer of an entry with an asserted pause bit
from CFIFO n .
• In level trigger mode, when CFIFO n is in the TRIGGERED state, PF n is set when CFIFO status changes from
TRIGGERED due to the detection of a closed gate.
An interrupt routine, generated due to the asserted PF, can be used to verify if a complete scan of the user-defined
command queue was performed. If a closed gate is detected while no command transfers are taking place, it has an
immediate effect on the CFIFO status. If a closed gate is detected while a command transfer to an on-chip ADC is
taking place, it only affects the CFIFO status when the transfer completes. If a closed gate is detected during the
serial transmission of a command to the external device, it has no effect on the CFIFO status until the transmission
completes.
The transfer of entries bound for the on-chip ADCs is considered completed when they are stored in the appropriate
ADC command buffer. The transfer of entries bound for the external device is considered completed when the serial
transmission of the entry is completed. In software trigger mode, PF
n is never asserted.
If PIE n (Refer to Section 18.3.2.7, “eQADC Interrupt and eDMA Control Registers 0–5 (EQADC_IDCRn) ”) and PF n
are asserted, an interrupt is generated. Writing a 1 clears the PF n . Writing a 0 has no effect. Refer to
Section 18.4.3.6.3, “Pause Status ,” for more information on pause flag.
0 Entry with asserted pause bit was not transferred from CFIFO n (CFIFO in edge trigger mode), or CFIFO status
did not change from the TRIGGERED state due to detection of a closed gate (CFIFO in level trigger mode).
1 Entry with asserted pause bit was transferred from CFIFO n (CFIFO in edge trigger mode), or CFIFO status
changes from the TRIGGERED state due to detection of a closed gate (CFIFO in level trigger mode).
Note: In edge trigger mode, an asserted PF n only implies that the eQADC has finished transferring a command with
an asserted pause bit from CFIFO n . It does not imply that result data for the current command and for all
previously transferred commands has been returned to the appropriate RFIFO.
Note: In software or level trigger mode, when the eQADC completes the transfer of an entry from CFIFO n with an
asserted pause bit, PF n is not set and commands continue to transfer without pausing.
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EOQF n
End-of-queue flag n . Indicates that an entry with an asserted EOQ bit was transferred from CFIFO n to the on-chip
ADCs or to the external device. Refer to Section 18.4.1.2, “Message Format in eQADC ,” for details about command
message formats. When the eQADC completes the transfer of an entry with an asserted EOQ bit from CFIFO n ,
EOQF n is set. The transfer of entries bound for the on-chip ADCs is considered completed when they are stored in
the appropriate command buffer. The transfer of entries bound for the external device is considered completed when
the serial transmission of the entry is completed. If the EOQIE
n bit (Refer to Section 18.3.2.7, “eQADC Interrupt and
eDMA Control Registers 0–5 (EQADC_IDCRn) ”) and EOQF n are asserted, an interrupt is generated. Writing a 1
clears the EOQF n bit. Writing a 0 has no effect. Refer to Section 18.4.3.6.2, “Command Queue Completion Status ,”
for more information on end-of-queue flag.
0 Entry with asserted EOQ bit was not transferred from CFIFO
n
1 Entry with asserted EOQ bit was transferred from CFIFO n
Note: An asserted EOQF n only implies that the eQADC has finished transferring a command with an asserted EOQ
bit from CFIFO n . It does not imply that result data for the current command and for all previously transferred
commands has been returned to the appropriate RFIFO.
Table 18-12. EQADC_FISR n Field Descriptions (continued)
Field Description