Freescale Semiconductor MPC5565, Reference Manual

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Nexus
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 24-83
24.14.2.11 IEEE
®
1149.1 (JTAG) Test Access Port
The NXDM module uses the IEEE
®
1149.1 TAP controller for accessing Nexus resources. The JTAG
signals themselves are shared by all TAP controllers on the device. Refer to Chapter 23, “IEEE 1149.1 Test
Access Port Controller (JTAGC) for more information on the JTAG interface.
The NXDM modules implements a 4-bit instruction register (IR). The valid instructions and method for
register access are outlined in
Section 24.7.2.3, “IEEE‚ 1149.1-2001 (JTAG) TAP
.”
24.14.2.11.1 NXDM JTAG DID Register
This JTAG DID register that is included in the NXDM module provides key development attributes to the
development tool concerning the NXDM block. The register is accessed through the standard JTAG IR/DR
paths. Refer to
Chapter 22, “Voltage Regulator Controller (VRC) and POR Module .”
24.14.2.11.2 Enabling the NXDM TAP Controller
Assertion of a power-on-reset signal or assertion of the JCOMP pin resets all TAP controllers on the
device. Upon exit from the test-logic-reset state, the IR value is loaded with the JTAG DID. When the
NXDM TAP is accessed, this information will help the development tool obtain information about the
Nexus module it is accessing, such as version, sequence, feature set, and so forth.
Access: R/W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PRN DC PIN MIC 1
W
Reset 0 0 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1
Figure 24-64. NXDM JTAG DID Register
Table 24-54. NXDM JTAG DID Field Descriptions
Field Description
31–28
PRN
1
1
The revision number is initially 0 and could change in the future.
Embedded part revision number (0x0)
27–22
DC
Freescale design center ID number (0x1F)
21–12
PIN
NXDM module part identification number, defines the features set. (0x60)
11–1
MIC
Manufacturer identity code
0x00E Freescale
0 Fixed per JTAG 1149.1
1 Always set