Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Time Processing Unit (eTPU)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
17-22 Freescale Semiconductor
Address: Base + 0x0000_0014 (eTPU A) Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
FEND MDIS
0 STF 0 0 0 0 HLTF 0 0 0 0
FPSCK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CDFC
0 0 0 0 0 0 0 0 0
ETB
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 17-9. eTPU Engine Configuration Register (ETPU_ECR)
Table 17-10. ETPU_ECR Field Descriptions
Field Description
0
FEND
Force end. Assertion terminates any current running thread as if an END instruction have been executed. For more
information, refer to the
eTPU Reference Manual .
0 Normal operation.
1 Terminates current thread.
This bit is self-negating.
1
MDIS
Module disable internal stop. This is the low power stop bit. When MDIS is set, the engine shuts down its internal
clocks. TCR1 and TCR2 cease to increment, and input sampling stops. The engine asserts the stop flag (STF) bit
to indicate that it has stopped. However, the BIU continues to run, and the host can access all registers except for
the channel registers
1
and writes to time base registers. For more information on channel registers, refer to
Section 17.4.6, “Channel Configuration and Control Registers .” After MDIS is set, even before STF asserts, data
read from the channel registers is not meaningful, a Bus Error is issued, and writes are unpredictable. When the
MDIS bit is asserted while the microcode is executing, the eTPU stops when the thread is complete.
0 eTPU engine runs.
1 Commands engine to stop its clocks.
Stop completes on the next system clock after the stop condition is valid. The MDIS bit is write-protected when
ETPU_MCR[VIS]=1.
Note: After the MDIS has been switched from 1 to 0 or vice-versa, do not switch its value again until STF is switched
to the same value.
2 Reserved.
3
STF
Stop flag bit. Each engine asserts its stop flag (STF) to indicate that it has stopped. Only then the host can assume
that the engine has actually stopped. The eTPU system is fully stopped when the STF bits of both eTPU engines
are asserted. The engine only stops when any ongoing thread is complete in this case.
0 The engine is operating.
1 The engine has stopped (after the local MDIS bit has been asserted).
Summarizing engine stop conditions, which STF reflects:
STF_A:= (after stop completed) MDIS_A
STF_B:= (after stop completed) MDIS_B
STF_A and STF_B mean STF bit from engine A and STF bit from engine B respectively.
4–7 Reserved.