Enhanced Serial Communication Interface (eSCI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
20-32
Freescale Semiconductor
(ESCI
x
_CR1) puts the receiver into the standby state, which disregards all receiver interrupts tar. The eSCI
loads the received data into the ESCI
x
_DR, but does not set the receive data register full (RDRF) flag.
The transmitting device can address messages to selected receivers by including addressing information
(address bits) in the initial frame or frames of each message. Refer to section
,” for an example of address bits.
The WAKE bit in eSCI control register 1 (ESCI
x
_CR1) determines how the eSCI is brought out of the
standby state to process an incoming message. The WAKE bit enables either idle line wake-up or address
mark wake-up.
20.4.5.6.1
Idle Input Line Wake-up (WAKE = 0)
Using the receiver idle input line wake-up method allows an idle condition on the RXD signal clears the
ESCI
x
_CR1[RWU] bit and wakes up the eSCI. The initial frame or frames of every message contain
addressing information. All receivers evaluate the addressing information, and receivers for which the
message is addressed process the frames that follow. Any receiver for which a message is not addressed
can set its RWU bit and return to the standby state. The RWU bit remains set and the receiver remains on
standby until another idle character appears on the RXD signal.
Idle line wake-up requires that messages be separated by at least one idle character and that no message
contains idle characters.
The idle character that wakes a receiver does not set the receiver idle bit, ESCI
x
_SR[IDLE], or the receive
data register full flag, RDRF.
The idle line type bit, ESCI
x
_CR1[ILT], determines whether the receiver begins counting logic 1s as idle
character bits after the start bit or after the stop bit.
20.4.5.6.2
Address Mark Wake-up (WAKE = 1)
Using the address mark wake-up method allows a logic 1 in the most significant bit (MSB) position of a
frame to clear the RWU bit and wake-up the eSCI. The logic 1 in the msb position marks a frame as an
address frame that contains addressing information. All receivers evaluate the addressing information, and
the receivers for which the message is addressed process the frames that follow. Any receiver for which a
message is not addressed can set its RWU bit and return to the standby state. The RWU bit remains set and
the receiver remains on standby until another address frame appears on the RXD signal.
The logic 1 msb of an address frame clears the receiver’s RWU bit before the stop bit is received and sets
the RDRF flag.
Address mark wake-up allows messages to contain idle characters but requires that the msb be reserved
for use in address frames.
NOTE
With the WAKE bit clear, setting the RWU bit after the RXD
signal has been
idle can cause the receiver to wake-up immediately.
Summary of Contents for MPC5565
Page 18: ...MPC5565 Microcontroller Reference Manual Devices Supported MPC5565 MPC5565 RM Rev 1 0 09 2007...
Page 34: ...MPC5565 Reference Manual Rev 1 0 Freescale Semiconductor 15...
Page 35: ...MPC5565 Reference Manual Rev 1 0 16 Freescale Semiconductor...
Page 553: ...Flash Memory MPC5565 Microcontroller Reference Manual Rev 1 0 13 38 Freescale Semiconductor...
Page 559: ...SRAM MPC5565 Microcontroller Reference Manual Rev 1 0 14 6 Freescale Semiconductor...
Page 973: ...Preface MPC5565 Microcontroller Reference Manual Rev 1 0 21 36 Freescale Semiconductor...
Page 1153: ...Calibration MPC5565 Microcontroller Reference Manual Rev 1 0 B 8 Freescale Semiconductor...