Freescale Semiconductor MPC5565, Reference Manual

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Flash Memory
MPC5565 Microcontroller Reference Manual, Rev. 1.0
13-22 Freescale Semiconductor
Access protections can be applied on a per-master basis for both reads and writes to support security and
privilege mechanisms.
13.4.1.1 FBIU Basic Interface Protocol
The Flash BIU interfaces to the flash array by driving addresses and read or write enable signals to the
flash memory interface unit. The access time of the flash is determined by the settings of the wait state
control bits in the FLASH_BIUCR, as well as the pipelining of addresses.
The Flash BIU also has the capability of extending the normal system bus access timing by inserting
additional primary (initial access) wait states for reads and burst reads. This capability is provided to allow
emulation of other memories which have different access time characteristics.
13.4.1.2 FBIU Access Protections
The Flash BIU provides hardware configurable access protections for both read and write cycles from
masters. It allows restriction of read and write requests on a per-master basis. The FBIU also supports
software configurable access protections. Detection of a protection violation results in an error response
from the Flash BIU to the system bus.
13.4.1.3 Flash Read Cycles—Buffer Miss
Read data is normally stored in the least-recently updated line read buffer in parallel with the requested
data being forwarded to the system bus.
13.4.1.4 Flash Read Cycles—Buffer Hit
Single clock read responses to the system bus are possible with the Flash BIU when the requested read
access is buffered.
13.4.1.5 Flash Access Pipelining
Accesses to the flash array can be pipelined by driving a subsequent access address and control signals
while waiting for the current access to complete. Pipelined access requests are always run to completion
and are not aborted by the Flash BIU. Request pipelining allows for improved performance by reducing
the access latency seen by the system bus master. Access pipelining can be applied to both read and write
cycles by the flash array.
13.4.1.6 Flash Error Response Operation
The flash array can terminate a requested access with an error. This can occur due to an uncorrectable ECC
error, an access control violation, or because of improper access sequencing during program/erase
operations. When an error response is received, the Flash BIU marks a line read buffer as invalid. An error
response can be signaled on read or write operations.