Freescale Semiconductor MPC5565, Reference Manual

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Interrupt Controller (INTC)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 10-37
In Section 10.5.10, “Examining LIFO contents:”
Added: “Normally you do not need to know the contents of the LIFO, or even how deep the LIFO is nested. Although the LIFO
contents are not memory mapped, you can read the contents by popping the LIFO and reading the PRI field in the INTC
current priority register (INTC_CPR). Disabling processor recognition of interrupts while examining the LIFO contents
provides a coherent view of the preempted priorities. The code sequence is:
pop_lifo:
store to INTC_EOIR
load INTC_CPR, examine PRI, and store onto stack
if PRI is not zero or value when interrupts were enabled, branch to pop_lifo
When you are finished examining the LIFO contents, you can restore it in software vector mode using the following code
sequence. In hardware vector mode, reading the INTC_IACKR does not push the INTC_CPR[PRI] onto the LIFO, therefore
the LIFO contents cannot be restored in hardware vector mode.
push_lifo:
load stacked PRI value and store to INTC_CPR
load INTC_IACKR
if stacked PRI values are not depleted, branch to push_lifo
NOTE
Reading the INTC_IACKR acknowledges the interrupt request to the processor and updates the INTC_CPR[PRI] with the
priority of the preempting interrupt request. If the processor recognition of interrupts is disabled during the LIFO restoration,
interrupt requests to the processor can go undetected. However, since the peripheral or software settable interrupt requests
are not cleared, the peripheral interrupt request to the processor re-asserts when INTC_CPR[PRI] is lower than the priorities
of those peripheral or software settable interrupt requests.
Throughout the chapter, replaced “priority inversion” with “scheduling inefficiencies” as follows:
Section 10.5.5.1, “Elevating Priority
• From: "After they release the resource, they must lower the PRI value in INTC_CPR to prevent further priority inversion."
• To: "After they release the resource, the PRI value in INTC_CPR can be lowered."
• From: "Using the PCP instead of disabling processor recognition of all interrupts reduces the priority inversion time when
accessing a shared resource."
• To: "Using the PCP instead of disabling processor recognition of all interrupts eliminates the time when accessing a shared
resource that all higher priority interrupts are blocked."
Section 10.5.6, “Selecting Priorities According to Request Rates and Deadlines
Added the acronyms RMS and DMS for ‘rate monotonic scheduling’ and ‘deadline monotonic scheduling.’
• From: "Reducing the number of priorities does cause some priority inversion which reduces the processor's ability to meet
its deadlines. It also allows easier management of ISRs with similar deadlines that share a resource. They can be placed
at the same priority without any further priority inversion, and they do not need to use the PCP to access the shared
resource"
• To: "Reducing the number of priorities does reduce the processor's ability to meet its deadlines. However, it also allows
easier management of ISRs with similar deadlines that share a resource. They do not need to use the PCP to access the
shared resource."
Section 10.5.7.1, “Scheduling a Lower Priority Portion of an ISR
• From: "Therefore, executing this later portion which does not need to be executed at this higher priority can block the
execution of ISRs which do not have a higher priority than the earlier portion of the ISR but do have a higher priority than
what the later portion of the ISR needs. This priority inversion reduces the processor's ability to meet its deadlines."
• To: "Therefore, executing this later portion which does not need to be executed at this higher priority can prevent the
execution of ISRs which do not have a higher priority than the earlier portion of the ISR but do have a higher priority than
what the later portion of the ISR needs. This preemptive scheduling inefficiency reduces the processor's ability to meet its
deadlines."
• From: "This software settable interrupt request, which usually will have a lower PRIn value in the INTC_PSRn, therefore
will not cause priority inversion."
• To: "This software settable interrupt request, which usually will have a lower PRIn value in the INTC_PSRn, therefore will
not cause preemptive scheduling inefficiencies."
Table 10-11. Changes Between MPC5565RM Revisions 0.1 and 1 (continued)