Freescale Semiconductor MPC5565, Reference Manual

Page: 6 / 1153

Addendum for Revision 1.0
MPC5565 Reference Manual Addendum, Rev. 2
Freescale Semiconductor 5
Table A-2, “MPC5565
Detailed Register
Map”/Page A-23
Correct names of peripheral bridge B control registers by adding underscore (PBRIDGEB_ x
becomes PBRIDGE_B_ x ).
Table 1. MPC5565RM Rev 1.0 addendum (continued)
Location Description
Register Description Register Name
Used
Size
Address
Peripheral bridge B master privilege
control register PBRIDGE_B_MPCR 32-bit Base + 0x0000
Reserved — — Base +
(0x0004-0x001F)
Peripheral bridge B peripheral access
control register 0 PBRIDGE_B_PACR0 32-bit Base + 0x0020
Reserved — — Base +
(0x0024-0x0027)
Peripheral bridge B peripheral access
control register 2 PBRIDGE_B_PACR2 32-bit Base + 0x0028
Reserved — — Base +
(0x002C-0x003F)
Peripheral bridge B off-platform
peripheral access control register 0 PBRIDGE_B_OPACR0 32-bit Base + 0x0040
Peripheral bridge B off-platform
peripheral access control register 1 PBRIDGE_B_OPACR1 32-bit Base + 0x0044
Peripheral bridge B off-platform
peripheral access control register 2 PBRIDGE_B_OPACR2 32-bit Base + 0x0048
Peripheral bridge B off-platform
peripheral access control register 3 PBRIDGE_B_OPACR3 32-bit Base + 0x004C
Reserved — — (Base + 0x0050)-
0xFFF0_3FFF)